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general description the max9979 fully integrated, high-performance, dual-channel pin electronics integrates multiple automatic test equipment (ate) functions into a single ic, including dri- ver/comparator/load (dcl), parametric measurement unit (pmu), and built-in (16-bit) level-setting digital-to-analog converters (dacs). the device is ideal for memory and soc tester applications. each channel includes a four- level pin driver, window comparator, differential compara- tor, dynamic clamps, a versatile pmu, an active load, a high-voltage (vhh) programmable level, and 14 indepen- dent level-setting dacs. the max9979 features program- mable cable-droop compensation for the driver output and for the comparator input, adjustable driver output resistance that allows optimal performance over typical data-path transmission-line variations, slew-rate adjust- ment, and a programmable high-voltage driver output. the max9979 driver features a wide 8v (-1.5v to +6.5v) high-speed operating voltage range and a vhh program- mable range of up to +13v. operation modes include high-impedance, active-termination (3rd-level drive) and vhh (4th-level drive) modes. the device is highly linear even at low voltage swings. the driver provides high- speed differential control inputs compatible with most high-speed logic families. the window comparators pro- vide extremely low timing variation over changes in slew rate, pulse width, and overdrive voltage. in high-imped- ance mode, the max9979 features dynamic clamps that dampen high-speed device-under-test (dut) waveforms. the 20ma active load facilitates fast contact testing when used in conjunction with the comparators, and functions as a pullup/pulldown for open-drain/collector dut out- puts. the pmu offers five current ranges from 2a to 50ma and can force and measure current or voltage. an spi?-compatible serial interface configures the max9979. the max9979 is available in a small footprint, 68-pin (10mm x 10mm x 1mm) tqfn-ep-idp package with exposed pad on the top for easy heat removal. power dis- sipation is 1.2w per channel (typ) over the full operating voltage range with the active load disabled. the max9979 operates over an internal die temperature range of +40c to +100c and provides a temperature monitor output. applications memory ate testerssoc ate testers features ? high speed: 1.1gbps at 1v p-p ? extremely low power dissipation: 1.2w/channel(active load disabled) ? wide voltage range: -1.5v to +6.5v and up to 13vvhh ? wide voltage swing range: 50mv p-p to 13v p-p ? low-leak mode: 10na max ? integrated termination-on-the-fly (3rd-leveldrive) ? integrated vhh high voltage (4th-level drive) ? integrated voltage clamps ? integrated 20ma active load ? integrated per-pin pmu ? integrated level-setting caldacs ? programmable cable-droop compensation forboth driver output and comparator input ? programmable driver output impedance ? four slew-rate settings for driver output ? analog measure bus ? very low timing dispersion ? minimal external component count ? spi-compatible serial control interface ? 68-pin thermally enhanced tqfn package withtop-side heat removal max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ________________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin configuration and typical operating circuit appear at end of data sheet. spi is a trademark of motorola, inc. + denotes a lead(pb)-free/rohs-compliant package. ordering information * ep-idp = exposed pad, inverted die pad. part temp range pin-package max9979kctk+ 0c to +70c 68 tqfn-ep-idp* 19-4134; rev 6; 8/11 downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 2 _______________________________________________________________________________________ absolute maximum ratingselectrical characteristics (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ............................................................-0.3v to +11v v ee to gnd............................................................-5.5v to +0.3v v cc to v ee ...........................................................-0.3v to +16.5v v dd to dgnd ........................................................-0.3v to +5.2v v hhp to gnd ..........................................................-0.3v to +19v dgnd to gnd ....................................................................0.3v ctv_, bv_ to gnd....................................................-0.3v to +5v data_, ndata_, rcv_, nrcv_ to gnd..............................(v ee - 0.3v) to (v bv_ + 0.3v) ch_, nch_, cl_, ncl_ to gnd..............-1.5v to (v ctv_ + 0.3v) current into ch_, nch_, cl_, ncl_ ................................35ma data_ to ndata_, rcv_ to nrcv_ .....................................1v dut_, pmu-f, pmu-s, sense_ to gnd (non-vhh mode) ...........................(v ee - 0.3v) to (v cc + 0.3v) dut_, pmu-f, pmu-s, sense_ to gnd (vhh mode).......................................................-3.5v to +13.5v sclk, din, cs , rst , load to gnd ..........-0.3v to (v dd + 0.3v) lleakp_ , hizmeasp_ , envhhp_ , duthi_, dutlo_, to gnd......................................-0.3v to (v dd + 0.3v) temp to gnd .................................................................0 to v cc meas_ to gnd.................................(v ee - 0.3v) to (v cc + 0.3v) ref to gnd..............................................-0.3v to (2.6v + v dgs ) current into sclk, din, cs , rst , load .........................30ma current into lleakp_ , hizmeasp_ , envhhp_ , duthi_, dutlo_ ...........................................................30ma pmu-f continuous current...............................................35ma pmu-f peak current.........................................................70ma pmu-s continuous current ................................................1ma pmu-s peak current.........................................................20ma dgs to gnd .......................................................................0.3v dut_, sense_ short-circuit duration to v cc , v ee ................................................continuous power dissipation (t a = +70c)* max9979kctk (derate 125mw/c above +70c) .............10w storage temperature range .............................-65c to +150c maximum junction temperature .....................................+150c lead temperature (soldering, 10s) .................................+300c * dissipation wattage values are based on still air with no heatsink. actual maximum power dissipation is a function of heat extr action technique and may be substantially higher. * *package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units driver dc characteristics (r l 10m , unless otherwise noted; includes dac error) v dhv v dlv_ = -1.5v, v dtv_ = 1.5v -1.45 to +6.50 v dlv v dhv_ = 6.5v, v dtv_ = 1.5v -1.50 to +6.45 output-voltage range v dtv v dhv_ = 6.5v, v dlv_ = -1.5v (note 2) -1.50 +6.50 v v dhv v dhv_ = 3v, v dlv_ = -1.5v, v dtv_ = 1.5v 5 v dlv v dlv_ = 0v, v dhv_ = 6.5v, v dtv_ = 1.5v 5 output offset voltage v dtv v dtv_ = 1.5v, v dhv_ = 6.5v, v dlv_ = -1.5v 5 mv output-voltage temperaturecoefficient (notes 3, 4) dhv_, dlv_, dtv_ 75 500 v/c package thermal characteristics** tqfn junction-to -case thermal resistance ( ja )...............8.0c/w junction-to-ambient thermal resistance ( jc )......................0.3c/w downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs _______________________________________________________________________________________ 3 electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units a dhv_ v dlv_ = -1.5v, v dtv_ = 1.5v, v dhv_ = 0v and 4.5v 0.998 1 1.002 a dlv v dhv_ = 6.5v, v dtv_ = 1.5v, v dlv_ = 0v and 4.5v 0.998 1 1.002 gain a dtv v dhv_ = 6.5v, v dlv_ = -1.5v, v dtv_ = 0v and 4.5v 0.998 1 1.002 v/v v dlv_ = -1.5v, v dtv_ = 1.5v, v dhv_ = 0v, 0.75v, 1.5v, 2.25v, 3v 2 v dhv_ = 6.5v, v dtv_ = 1.5v, v dlv_ = 0v, 0.75v, 1.5v, 2.25v, 3v 2 0 to 3v relative tocalibration points at 0 and 3v v dlv_ = -1.5v, v dhv_ = 6.5v, v dtv_ = 0v, 0.75v, 1.5v, 2.25v, 3v 2 v dlv_ = -1.5v, v dtv_ = 1.5v, v dhv_ = -1v and 6v 4.5 v dhv_ = 6.5v, v dtv_ = 1.5v, v dlv_ = -1v and 6v 4.5 -1v to 6v relativeto calibration points at 0 and 3v v dlv_ = -1.5v, v dhv_ = 6.5v, v dtv_ = -1v and 6v 4.5 v dlv_ = -1.5v, v dtv_ = 1.5v, v dhv_ = -1.25v and 6.5v 6 v dhv_ = 6.5v, v dtv_ = 1.5v, v dlv_ = -1.5v and 6.25v 6 linearity error full range relativeto calibration points at 0 and 3v v dlv_ = -1.5v, v dhv_ = 6.5v, v dtv_ = -1.5v and 6.5v 6 mv downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 4 _______________________________________________________________________________________ electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units dhv_ to dlv_ v dlv_ = 0v, v dtv_ = 1.5v, v dhv_ = 0.2v and 6.5v 7 dlv_ to dhv_ v dhv_ = 5v, v dtv_ = 1.5v, v dlv_ = -1.5 and 4.8v 7 dtv_ to dlv_ anddhv_ v dhv_ = 3v, v dlv_ = 0v, v dtv_ = -1.5v and 6.5v 2 dhv_ to dtv_ v dtv_ = 1.5v, v dlv_ = 0v, v dhv_ = 1.6v and 3v 3 crosstalk dlv_ to dtv_ v dtv_ = 1.5v, v dhv_ = 3v, v dlv_ = 0 and 1.4v 3 mv term voltage dependence ondata_ v dtv_ = 1.5v, v dhv_ = 3v, v dlv_ = 0v, data_ = 0 and 1 2 mv dhv_ v dhv_ = 3v 40 dlv_ v dlv_ = 0v 40 dc power-supply rejection(note 5) dtv_ v dtv_ = 1.5v 40 db data_ = 1, v dut_ = -1.5v +60 +110 dc drive current limit v dhv_ = 6.5v, v dlv_ = -1.5v data_ = 0, v dut_ = 6.5v -110 -60 ma dc output resistance (note 6) 48 50 52 d ata_ = 1, v d h v _ = 3v , v d lv _ = 0v , v d tv _ = 1.5v , i d u t _ = 1m a, 8m a, 15m a, 40m a 12 dc output resistance variation(note 7) data_ = 0, v d h v _ = 3v , v d lv _ = 0v , v d tv _ = 1.5v , i d u t _ = - 1m a, - 8m a, - 15m a, - 40m a 12 adjustable output resistancerange r o = 0xf vs. r o = 0x8 and r o = 0x0 vs. r o = 0x8, resolution of 0.36 (note 6) 2.5 downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs _______________________________________________________________________________________ 5 electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units ac characteristics (r dut _ = 50 to ground) (note 8) dynamic drive current (note 9) 130 ma cable-droop compensation off, v dlv_ = 0v, v dhv_ = 0.1v 30 cable-droop compensation off, v dlv_ = 0v, v dhv_ = 1v 40 cable-droop compensation off, v dlv_ = 0v, v dhv_ = 3v 50 drive-mode overshoot cable-droop compensation off, v dlv_ = 0v, v dhv_ = 5v 50 mv v dlv_ = 0v, v dhv_ = 3v, cdrp_ = 0b000 0 cable-droop compensation v dlv_ = 0v, v dhv_ = 3v, cdrp_ = 0b111 10 % termination-mode overshoot cable-droop compensation off (note 10) 0 mv to within 100mv, v dhv_ = 5v, v dlv_ = 0v 0.25 1 to within 50mv, v dhv_ = 3v, v dlv_ = 0v 0.25 1 settling time (notes 4, 11) to within 50mv, v dhv_ = 0.5v, v dlv_ = 0v 0.25 1 ns timing characteristics (notes 8, 12) data to output, v dhv_ = 3v, v dlv_ = 0v (note 13) 1 1.9 4 drive to term, term to drive (notes 4, 14) 1.7 2.7 3.7 propagation delay drive to high impedance, high impedanceto drive, v dhv_ = 1v, v dlv_ = -1v (notes 4, 15) 1.4 2.4 3.4 ns t lh vs. t hl (note 4) 40 80 drivers within package, same edge 40 ps drive to high impedance vs. highimpedance to drive, v dhv_ = 1v, v dlv_ = -1v (note 16) 0.5 high impedance vs. data 0.5 drive to term vs. term to drive, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v (note 17) 0.3 propagation-delay match terminate vs. data 0.8 ns propagation-delay channelmatch differential mode, v dhv_ = 1v, v dlv_ = 0v, channel 1 inverted, differential0 = 1,invert1 = 1 40 ps downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units propagation-delay temperaturecoefficient v dhv_ = 3v, v dlv_ = 0v (note 4) 3 5 ps/c v dhv_ = 1v, v dlv_ = 0v, 1ns to 24ns pulsewidth (note 4) 25 60 v dhv_ = 3v, v dlv_ = 0v, 1ns to 24ns pulsewidth (note 4) 35 60 change vs. pulsewidth (note 18) v dhv_ = 5v, v dlv_ = 0v, 1.5ns to 23.5nspulse width 100 propagation-delay change peak-to-peak change vs. common mode,v dhv_ - v dlv_ = 1v, v dhv_ = 0 to 6v, using a dc-blocking capacitor (note 4) 50 60 ps 0.2v p-p programmed, v dhv_ = 0.2v, v dlv_ = 0v, 20% to 80% 275 1v p-p programmed, v dhv_ = 1v, v dlv_ = 0v, 10% to 90% 330 450 550 3v p-p programmed, v dhv_ = 3v, v dlv_ = 0v, 10% to 90%, trim condition 500 650 800 rise-and-fall time 5v p-p programmed, v dhv_ = 5v, v dlv_ = 0v, 10% to 90% (note 4) 800 1000 1200 ps 0.2v p-p programmed, v dhv_ = 0.2v, v dlv_ = 0v, 20% to 80% 40 1v p-p programmed, v dhv_ = 1v, v dlv_ = 0v, 10% to 90% 50 130 3v p-p programmed, v dhv_ = 3v, v dlv_ = 0v, 10% to 90% 50 200 rise-and-fall time matching 5v p-p programmed, v dhv_ = 5v, v dlv_ = 0v, 10% to 90% 50 ps electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs _______________________________________________________________________________________ 7 parameter symbol conditions min typ max units sc1 = 0, sc0 = 1,v dhv_ = 3v, v dlv_ = 0v, 20% to 80% 75 sc1 = 1, sc0 = 0,v d h v _ = 3v , v d lv _ = 0v , 20% to 80% 50 slew rate relative to sc1 =sc0 = 0 s c 1 = 1, s c 0 = 1, v d h v _ = 3v , v d lv _ = 0v , 20% to 80% 25 % 0.2v p-p programmed, v dhv_ = 0.2v, v dlv_ = 0v (note 19) 800 1v p - p p r og r am m ed , v d h v _ = 1v , v d lv _ = 0v (note 19) 950 3v p - p p r og r am m ed , v d h v _ = 3v , v d lv _ = 0v (notes 4, 19) 1000 1250 minimum pulse width positive ornegative 5v p - p p r og r am m ed , v d h v _ = 5v , v d lv _ = 0v (note 19) 1300 ps 0.2v p-p programmed, v dhv_ = 0.2v, v dlv_ = 0v 1100 1v p - p p rog r am m ed, v d h v_ = 1v , v d lv_ = 0v 900 3v p - p p rog r am m ed, v d h v_ = 3v , v d lv_ = 0v 800 to 95% p-p (note 20) 5v p - p p rog r am m ed, v d h v_ = 5v , v d lv_ = 0v 680 0.2v p - p p rog r am m ed, v d h v_ = 0.2v, v d lv_ = 0v 1200 1v p - p p rog r am m ed, v d h v_ = 1v , v d lv_ = 0v 1100 3v p - p p rog r am m ed, v d h v_ = 3v , v d lv_ = 0v 900 data rate to 90% p-p (note 21) 5v p - p p rog r am m ed, v d h v_ = 5v , v d lv_ = 0v 720 mbps electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 8 _______________________________________________________________________________________ parameter symbol conditions min typ max units d r i ve to ter m , v d h v _ = 3v , v d lv _ = 0v , v d tv _ = 1.5v , m easur ed 10% to 90% of w avefor m 300 500 1000 rise-and-fall time ter m to d r i ve, v d h v _ = 3v , v d l v _ = 0v , v d t v _ = 1.5v , m easur ed 10% to 90% of w avefor m 300 600 850 ps high-speed comparators dc characteristics input-voltage range (notes 2, 22) -1.5 +6.5 v differential input voltage v dut_ - v chv_ , v dut_ - v clv_ (note 23) 8 v input offset voltage v dut_ = 1.5v 1 5 mv input-voltage temperaturecoefficient (notes 4, 24) 50 175 vc common-mode rejection ratio cmrr v dut_ = -1.5v, 6.5v (note 25) 50 55 db 0 to 3v, v dut_ = 0v, 1.5v, 3v 1 5 linearity error (note 26) ful l r ang e, v d u t _ = - 1.5v , 0v , 1.5v , 3v , 6.5v 1 10 mv power-supply rejection ratio psrr v dut_ = -1.5 and 6.5v (notes 5, 27) 50 66 db hyst0 hyst1 hyst2 000 0 001 2 010 4 011 6 100 8 101 1 0 110 1 2 hysteresis 111 1 5 mv ac characteristics (notes 4, 28, 29, 30) minimum pulse width (note 31) 0.50 0.65 ns propagation delay 0.5 0.9 1.5 ns propagation-delay temperaturecoefficient 1.7 ps/c propagation-delay match high/low vs. low/high, absolute value of delta for each comparator 10 25 ps propagation-delay dispersion vs.common-mode input -1.4v to +6.4v (note 32) 40 55 ps p - p propagation-delay dispersion vs.duty cycle 0.6ns to 24.4ns pulse width, relative to 5nspulse width 25 40 ps propagation-delay dispersion vs.slew rate 1v/ns to 6v/ns, relative to 2v/ns (note 33) 30 55 ps electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs _______________________________________________________________________________________ 9 parameter symbol conditions min typ max units v dtv_ = 0.5v, driver terminated (note 34) 1000 1500 equivalent 20C80 bandwidth driver high impedance 700 mhz cdrp = 0b000 0 cable-droop compensation,peaking 1v swing, rise/fall time =500ps, drv terminated cdrp = 0b111 10 % logic outputs (ch_, nch_, cl_, ncl_ collector output, r l = 50 internal pullup to ctv) termination voltage ctv _ 0 3.5 v output high current 0m a output low current 16 ma output-voltage compliance set by i out_ , r term_ and v ctv -0.5 ctv _ v differential rise time 20% to 80% (note 4) 200 400 ps differential fall time 20% to 80% (note 4) 200 400 ps termination resistor value ctv _ to ch_, nch_, cl_, ncl_ 48 52 output high voltage v oh with output resistors, r term to v ctv (note 56) ctv _ - 0.1 ctv _ - 0.02 ctv _ v output low voltage v ol with output resistors, r term to v ctv (note 56) ctv _ - 0.55 ctv _ - 0.4 ctv _ - 0.35 v output-voltage swing with output resistors, 50 nominal trim (note 56) 350 400 450 mv dynamic clamps cphv_ functional clamp range i dut _ = -1ma, v cplv_ = -1.5v (note 2) -0.3 +6.5 v cplv_ functional clamp range i dut _ = 1ma, v cphv_ = 6.5v (note 2) -1.5 +5.3 v cphv_ maximum programmablevoltage i dut _ = 0ma (note 23) 7.2 7.5 v cplv_ minimum programmablevoltage i dut _ = 0ma (note 23) -2.5 -2.2 v i d u t _ = - 1m a, v c p h v _ = 1.5v , v c p l v _ = - 1.5v 10 offset voltage i dut_ = 1ma, v cplv_ = 1.5v, v cphv_ = 6.5v 10 mv offset-voltage temperaturecoefficient v cphv_ = v cplv_ = 1.5v 0.5 mv/c i dut_ = -1ma, v cphv_ = 1.5v, v cplv_ = -1.5v (note 5) 40 power-supply rejection ratio i dut_ = +1ma, v cplv_ = 1.5v, v cphv_ = 6.5v (note 5) 40 db high clamp voltage gain v cphv_ = -0.3v, 6.5v 0.998 1.002 v/v low clamp voltage gain v cplv_ = -1.5v, 5.3v 0.998 1.002 v/v voltage-gain temperaturecoefficient 100 ppm/c electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 10 ______________________________________________________________________________________ parameter symbol conditions min typ max units i dut _ = -1ma, v cphv_ = -0.3v, 1.5v, 3.25v, 5v, 6.5v 30 linearity i dut _ = 1ma, v cplv_ = -1.5v, 0.5v, 2.25v, 4v, 5.3v 30 mv v cphv_ = 0v, v cplv_ = -1.5v, r l = 0 to 6.5v -120 -60 static output current v cplv_ = 5v, v cphv_ = 6.5v, r l = 0 to -1.5v 60 120 ma high clamp resistance v cphv_ = 0v, v cplv_ = -1.5v, i dut _ = -5ma and -15ma 48 55 low clamp resistance v cphv_ = 6.5v, v cplv_ = 0v, i dut _ = 5ma and 15ma 48 55 high clamp-resistance variation i dut _ = -20ma and -30ma, v cphv_ = 2.5v, v cplv_ = -1.5v (note 35) 5 low clamp-resistance variation i dut _ = 20ma and 30ma, v cplv_ = 2.5v, v cphv_ = 6.5v (note 35) 5 overshoot and undershoot (note 36) 700 mv parametric measurement unit (pmu) dc electrical characteristics force voltage (r l 10m , v in_ = 2.5v, unless otherwise noted) i dut_ = 0ma -1.5 +6.5 i dut_ = +fsr/2, range a -1.5 +4.5 i dut_ = +fsr/2, ranges bCe -1.5 +6.1 i dut_ = -fsr/2, range a 1.1 6.5 force-voltage output range(note 2) v in i dut_ = -fsr/2, ranges bCe -1.1 +6.5 v force-voltage offset error i dut_ = 0ma -5 +5 mv force-voltage psrr (note 5) -5 +5 mv/v force-voltage load regulation i dut_ = +fsr/2 to -fsr/2 using sense_ input 200 v force-voltage offsettemperature coefficient (note 37) 50 v/c force-voltage gain error v in = -1.5v to +6.5v, nominal gain = +1 -0.1 +0.1 % force-voltage gain temperaturecoefficient 10 ppm/c force-voltage linearity error v in = -1.5v, 0.5v, 2.5v, 4.5v, 6.5v (notes 38, 39) -0.02 +0.02 %fsr electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 11 parameter symbol conditions min typ max units force-voltage range switchingglitch from any two adjacent ranges, c dut_ = 100pf, i dut_ = (0.25 x fsr) of lower current range (note 4) 0.3 v measure current (measured at meas_ in fimi mode, v in_ = v iios = v dut_ = 2.5v) measure-current offset i mos (note 38) -1 +1 %fsr measure-current psrr i dut_ = 0ma (note 5) -0.05 +0.05 %fsr/v measure-current offsettemperature coefficient 20 p p mfs r/ c ranges a, b, c -1.0 +1.0 measure-current gain error i mge ranges d, e -1.1 +1.1 % ranges bCe 20 measure-current gaintemperature coefficient range a +100 ppm/c ranges bCe, i dut_ = -fsr/2, -fsr/4, 0, fsr/4, fsr/2 relative to end points -0.02 +0.02 range a, i dut_ = -30ma, -15ma, 0, 15ma, 30ma, relative to end points -0.03 +0.03 measure-current linearity error(note 38) i mler range a, i dut_ = -fsr/2, -fsr/4, 0, fsr/4, fsr/2 relative to end points -0.06 +0.06 %fsr v iiosmin = 2v (note 40) 6 +fsr measure output voltage v iiosmax = 4v (note 40) 8 v v iiosmin = 2v (note 40) -2 -fsr measure output voltage v iiosmax = 4v (note 40) 0 v rejection of output measure error due to common-mode sense voltage cmvr ler i d u t_ = 0m a, v in _ = - 1.5v to + 6.5v , p er cent fs r chang e at me as _ p er volt chang e at d u t_ 0.003 %fsr/v range e, r_e = 500k -2 +2 range d, r_d = 50k -20 +20 range c, r_c = 5k -200 +200 a range b, r_b = 500 -2 +2 measure-current range (note 2) range a, r_a = 20 (note 41) -50 +50 ma force current (v dut_ = v in_ = v iios = 2.5v, unless otherwise noted) v iiosmin = 2v 6 input-voltage range for settingforce current to +fsr/2 v iiosmax = 3.5v 7.5 v v iiosmin = 2v -2 input-voltage range for settingforce current to -fsr/2 v iiosmax = 3.5v -0.5 v current-sense amplifier offsetvoltage input relative to v dgs 2.0 2.5 3.5 v electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 12 ______________________________________________________________________________________ parameter symbol conditions min typ max units force-current offset (note 38) -0.1 +0.1 %fsr force-current offset psrr (note 5) -0.2 +0.2 %fsr/v force-current offset-temperature coefficient (note 37) 20 ppmfsr/ c force-current gain error v in_ = -1.5v and 6.5v -0.1 +0.1 % ranges bCe 20 force-current gain-temperature coefficient range a -100 ppm/c ranges bCe, v in_ = -1.5v, 0.5v, 2.5v, 4.5v, 6.5v relative to end points of i dut_ -0.025 +0.025 range a, idut_ 30ma, vin_ = 0v, 1v, 1.3v, 2.5v, 3.7v, 4.9v relative to end points of i dut_ -0.03 +0.03 force-current linearity error (notes 38, 39) range a, v in_ = -1.5v, 0.5v, 2.5v, 4.5v, 6.5v relative to end points of i dut_ -0.06 +0.06 %fsr rejection of output error due to common-mode dut_ voltage percent of fsr change of the force current per volt change in dut_, v dut_ = -1.5v to 6.5v 0.007 %fsr/v range e, r_e = 500k -2 +2 range d, r_d = 50k -20 +20 range c, r_c = 5k -200 +200 a range b, r_b = 500 -2 +2 force-current range (note 2) range a, r_a = 20 , (note 41) -50 +50 ma measure voltage (measured at meas_ in fvmv mode, v vios = 0, v dut_ = v in_ = v iios = 2.5v) measure-voltage offset -25 +25 mv measure-voltage psrr (note 5) -5 +5 mv/v measure-voltage offset temperature coefficient 100 v/c measure-voltage gain error v dut_ = -1.5v and 6.5v, nominal gain = +1 -1 +1 % measure-voltage gain- temperature coefficient 1 0 p p m / c measure-voltage linearity error v in_ = -1.5v, 0.5v, 2.5v, 4.5v, 6.5v relative to end points. (note 38) -0.02 +0.02 %fsr for v dut_ = 6.5v, measure voltage input range = -1.5v to 6.5v, v vios offsets the range at meas_ 6.5 + v vios measure output voltage (note 42) for v dut_ = -1.5v -1.5 + v vios v voltage sense amp offset voltage input v ios relative to dut ground (note 42) 0 1.5 v electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 13 parameter symbol conditions min typ max units force output range a, v in_ = -1.5v, v dut_ = 6.5v, clenable = 0 -100 -55 range b, v in_ = -1.5v, v dut_ = 6.5v, clenable = 0 -8 -3 range a, v in_ = 6.5v, v dut_ = -1.5v, clenable = 0 55 100 short-circuit current limit in fv mode range b, v in_ = 6.5v, v dut_ = -1.5v, clenable = 0 3 8 ma force-to-sense resistor r fs (note 4) 10 k sense input all modes except v hhp driver mode -1.5 +6.5 input-voltage range vhh_ driver-mode compliance, sense open (note 43) -1.5 +13.0 v input bias current v sense_ = -1.5v and 6.5v, sense input enabled -5 +5 na comparator inputs (v in_ = v iios = 2.5v, hysten = 0, unless otherise noted) maximum at v iios = 3.4v, mi mode +7.4 input-voltage range minimum at v iios = 2v, mi mode -2.2 v fimv offset voltage v dut_ = 2.5v (note 44) -5 +5 mv fvmi offset current ivmax_ = ivmin_ = 2.5v (note 44) -0.1 +0.1 %fsr hysteresis hysten = 1, functionally tested in mv mode 25 50 mv voltage clamps (fi mode, clenable_ = 1) clamp voltage range (note 45) -1.5 +6.5 v linear fi dut_ range fi loop not influenced when v dut_ 0.5v from voltage clamps v clamplo_ + 0.5 v clamphi_ - 0.5 v clamp voltage accuracy v clamphi_ = v clamplo_ = -1.5v, 0v, 1.5v, 2.5v, 4v, 5v, 6.5v -20 +20 mv current clamps (fv mode, clenable_ = 1) v clamphi_max clamp current = i clamphi_ = (v clamphi_ - v iios )/r range (sourcing) v iios + 1.3v input control voltage range v clamplo_min clamp current = i clamploi_ = (v clamplo_ - v iios )/ r range (sinking) v iios - 1.3v v electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 14 ______________________________________________________________________________________ parameter symbol conditions min typ max units range e, r_e = 500k -2.2 +2.2 range d, r_d = 50k -22 +22 range c, r_c = 5k -220 +220 a range b, r_b = 500 -2.2 +2.2 clamp current range (note 45) range a, r_a = 20 -55 +55 ma linear fv i dut_ range fv loop not influenced when i dut_ 10% fsr from current clamps i clamp lo_ + 10%fsr i clamphi_ - 10%fsr a clamp current accuracy | i c la m p h i _ | = | i c la m p lo_ = 0, ( 0.25 x fs r) , ( 0.50 x fs r) and ( 0.55 x fs r) , cal i b r ated at 0 and ( 0.50 x fs r) -0.5 +0.5 %fsr comparator outputs (note 46) output high voltage r pullup = 1k to v dd v dd - 0.2 v output low voltage r pullup = 1k to v dd 0.4 v high-impedance state leakagecurrent 1 a high-impedance state outputcapacitance 6p f ac electrical characteristics (v vios = 0v, v iios = 2.5v, c dut_ = c meas_ = 100pf, r dut_ = 4 x r range to 2.5v, unless otherwise noted; setting times are to 0.1%fsr) force voltage range e, r_e = 500k 140 range d, r_d = 50k 30 range c, r_c = 5k 20 30 v in_ = -1.5v, 6.5v range b, r_b = 500 20 settling time v in_ = -1v to +6.5v range a, r_a = 20 , r dut_ = 200 to 2.5v (note 41) 20 s maximum stable loadcapacitance 2500 pf force voltage/measure current range e, r_e = 500k 300 range d, r_d = 50k 40 range c, r_c = 5k 20 35 range b, r_b = 500 20 settling time range a, r_a = 20 , r dut_ = 200 to 2.5v (note 41) 20 s electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 15 parameter symbol conditions min typ max units range-change switching in addition to force-voltage and measure-current settling times, range a to range b (note 47) 20 s force current (measured at meas_ in fimi mode) range e, r_e = 500k 500 range d, r_d = 50k 100 range c, r_c = 5k 25 35 v in_ = -1.5v, +6.5v range b, r_b = 500 20 settling time v in_ = -1.1v to +4.1v range a, r_a = 20 r dut_ = 200 to 2.5v (note 41) 20 s force current/measure voltage (note 48) range e, r_e = 500k 1900 range d, r_d = 50k 200 range c, r_c = 5k 30 40 range b, r_b = 500 20 settling time range a, r_a = 20 , r dut_ = 200 to 2.5v (note 41) 20 s range-change switching in addition to force-current/measure-voltagesettling times, range a to range b. (note 47) 20 s sense input to measure output path (note 49) propagation delay measured at 90% of output, sense inputslew rate 2v/s 0.07 s measure output h i g h- im p ed ance leakag e c ur r ent v meas_ = -1.5v, 2.5v, 6.5v -10 +10 na hizmeasp_ true to high-impedance time r meas_ = 5k to gnd, v sense = 2.5v, measured from the 50% point ofhizmeasp_ to 90% of output 80 ns hizmeasp_ false to active time r meas_ = 5k to gnd, v sense = 2.5v, measured from the 50% point ofhizmeasp_ to 10% of output 40 ns maximum stable loadcapacitance 1000 pf force output lleakp_ true to low-leak time v in_ = 1v, r dut_ = r range_ to gnd, fvmi mode, measured from the 50% point oflleakp_ to 90% of output 0.3 s electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 16 ______________________________________________________________________________________ parameter symbol conditions min typ max units lleakp_ false to active time v in _ = 1v, r dut _ = r range _ to gnd, fvmi mode, measured from the 50% point oflleakp_ to 10% of output 0.3 s comparators (c cmp _ = 20pf, r pullup = 1k to v dd ) rise time 20% to 80% 35 ns fall time 80% to 20% 1.5 ns disable true to high impedance measured from the 50% point of cs (or load ) to 10% of the output 25 ns disable false to active measured from the 50% point of cs (or load ) to 90% of the output 20 ns active load dc characteristics (v vcom_ = 2.5v, v dhv_ = v dlv_ = 6v, unless otherwise noted) vcom_ voltage range vcom_ -1.5 +6.5 v vcom_ offset voltage i dut_ = 0ma 5 mv differential voltage range v dut_ - v vcom_ -8 +8 v offset voltage-temperaturecoefficient 100 v/c vcom_ voltage gain v vcom _ = 0, 4.5v 0.998 1 1.002 v/v vcom_ voltage-gaintemperature coefficient -10 ppm/c vcom_ linearity error v vcom _ = -1.5v, 0v, 1.5v, 3v, 4.5v, 6.5v relative to end points 3 15 mv vcom_ output-voltage power-supply rejection ratio (note 5) 40 db i source = i sink = 20ma 30 sink or source output resistance v dut _ = 3v, 6.5v with v vcom _ = -1.5v or v dut _ = -1.5v, 2v with v vcom _ = 6.5v i source = i sink = 1ma 250 k linear region output resistance i dut _ = 10ma 12 18 i source _ = i sink _ = 10ma, 80% commutation 400 dead-band 95% i source_ to 95% i sink_ , i source = i sink = 20ma 700 900 mv electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 17 parameter symbol conditions min typ max units source current (v dut_ = -1v, v vcom_ = 6v, v vldl_ = 0v, v vldh_ = 6v, unless otherwise noted) source current output range v vldh_ = 0 to 6v (note 2) 0 20 ma source current offset v vldh_ = 300mv (1ma) -20 +20 a source current programminggain v vldh_ = 0.3v, 5.4v (1ma, 18ma) 3.326 3.333 3.340 ma/v source current temperaturecoefficient -10 a/ o c source current power-supplyrejection ratio (note 5) 60 a/v source current linearity v vldh_ = 0v, 0.1v, 0.3v, 1.5v, 3v, 5.4v, 6v, relative to 0.3v and 5.4v 80 a sink current (v dut _ = 6v, v vcom _ = -1v, v vldl _ = 6v, v vldh _ = 0v, unless otherwise noted) sink current output range v vldl_ = 0 to 6v (note 2) 0 20 ma sink current offset v vldl_ = 300mv (1ma) -20 +20 a sink current programming gain v vldl_ = 0.3v, 5.4v (1ma, 18ma) 3.326 3.333 3.340 ma/v sink current temperaturecoefficient 10 a/c sink current power-supplyrejection ratio psrr (note 5) 60 a/v sink current linearity v vldl_ = 0v, 0.1v, 0.3v, 1.5v, 3v, 5.4v, 6v, relative to 0.3v and 5.4v 80 a ac characteristics (z l = 50 to gnd, v vldh_ = v vldl_ = 6v, tmsel_ = lddis_ = ldcal_ = 0) transition time to/from inhibit viarcv/nrcv t en measured from 50% crossing of rcv/nrvcto 10% level of output waveform; v vcom_ = -1.5v and 1.5v 2n s spike during enable/disabletransition v vcom_ = 0v (note 4) 200 300 mv temperature monitor nominal voltage t j = +70c, r l 10m 3.43 v temperature coefficient 10 mv/c output resistance 15 k digital i/o differential control inputs (data_, ndata_, rcv_, nrcv_) input high voltage -1.6 +3.5 v input low voltage -2.0 +3.1 v differential input voltage 0.15 1.0 v electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 18 ______________________________________________________________________________________ parameter symbol conditions min typ max units differential terminationresistance between rcv and nrcv, data, andndata, tested at i rcv_/nrcv_ = 4ma (note 50) 96 104 single-ended control inputs ( cs , sclk, din, rst , load , envhhp_ , lleakp_ , hizmeasp_ ) input high 2/3 x v dd v dd v input low -0.1 1/3 x v dd v input bias current -25 +25 a single-ended output (dout) output high i oh = 25a v dd - 0.15 v output low i ol = -25a dgnd+ 0.15 v serial port timing sclk frequency f 50 mhz sclk pulse-width high t ch 8n s sclk pulse-width low t cl 8n s cs low to sclk high setup t css0 3.5 ns sclk high to cs low hold t csh0 3.5 ns cs high to sclk high setup t css1 3.5 ns sclk high to cs high hold t csh1 3.5 ns din to sclk high setup t ds 3.5 ns din to sclk high hold t dh 3.5 ns cs high pulse width t cswh 40 ns load low pulse width t ldw 20 ns rst low pulse width t rst 20 ns cs high to load low hold time t cshld 20 ns sclk to dout delay t do 40 ns common functions operating voltage range (note 2) -1.5 +13.0 v v dut _ = 0v, 1.5v, 3v -2 +2 v clv _ = v chv _ = 6.5v, v dut _ = -1.5v -5 +5 dut_ high-impedance leakage v clv _ = v chv _ = -1.5v, v dut _ = 6.5v -5 +5 a electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 19 parameter symbol conditions min typ max units v dut _ = 0v, 1.5v, 3v, t j < +90c -10 +10 v clv _ = v chv _ = 6.5v, v dut _ = -1.5v, t j < +90c -10 +10 dut_ low-leak mode leakage v clv _ = v chv _ = -1.5v, v dut _ = 6.5v, t j < +90c -10 +10 na driver in terminate mode (note 4) 3.4 4.3 dut_ combined capacitance driver in high impedance, pmu in highimpedance 8 pf low-leakage enable time lleakp_ low to dut_ = low leak 20 s low-leakage disable time lleakp_ high to normal operation 20 s power supply positive supply voltage v cc 9.5 9.75 10.5 v negative supply voltage v ee -5.2 -4.75 -4.5 v logic supply voltage v dd 2.7 3.3 5.0 v v hhp supply voltage v hhp 17 17.5 18 v positive supply current i cc (note 51) 120 135 ma negative supply current i ee (note 51) 245 260 ma logic supply current i dd (note 51) 4.5 7 ma (note 51) 1.5 2.0 v hhp supply current i h vhh mode, no load 45 50 ma power dissipation per channel includes ctv power at v ctv1 = v ctv2 = 1.4v (note 51) 1.2 1.35 w analog inputs dut ground sense input range v dgs relative to agnd (note 52) -150 +150 mv input bias current v dgs = 0v -10 +10 a dhv_, dlv_, dtv_, cphv_, cplv_, vhh_ 0.985 0.990 1.005 gain all other levels and meas_ output 0.995 1.000 1.005 v/v 2.5v reference nominal voltage v ref (notes 53, 54) 2.5 v input bias current -2 +2 a analog bus (v dut _ = -1.5v to +6.5v, pmu-f = pmu-s = -1.5v to +6.5v, unless otherwise noted ) pmu-f switch i switch = 2.5ma, v dut_ = -1.25v, 2.50v, 6.25v 100 pmu-s switch i switch = 100a, v dut_ = -1.25v, 2.50v, 6.25v 2.5 k electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 20 ______________________________________________________________________________________ parameter symbol conditions min typ max units pmu-s switch i switch = 10a, v dut_ = 6.5v to 13v, v pmu-f = v pmu-s = 6.5v to 13v for v hh level calibration 5k pmu-f path current 30 ma pmu-f, pmu-s on-leakage f and s independent, other channelswitches off -10 5 +10 na pmu-f, pmu-s off-leakage -10 1 +10 na differential comparator (differential_ = 1) dc characteristics (v clv_ = v chv_ = 0v, unless otherwise noted) input-voltage range v dut0 , v dut1 (notes 22, 55) -1.5 +6.5 v differential threshold voltagerange clv, chv levels may be safely programmed beyondthis range -1 +1 v differential input voltage (notes 22, 23) -8 +8 v offset error v dut_ = 0v -5 +5 mv gain v dutn = 0v, v dutm = -1v, 1v 0.998 1 1.002 v/v linearity error relative to straightline from -1v to +1v v dutn = 0v, v dutm = -1v, -0.5v, 0, 0.5v, 1v -5 +5 mv hyst0 hyst1 hyst2 000 0 001 2 010 4 011 6 100 8 101 1 0 110 1 2 hysteresis 111 1 5 mv offset temperature coefficient v dutn = 0v and v dutm = -1v, 1v (note 4) -150 +150 v/c dc power-supply rejection ratio v dut_ = 1.5v (note 27) 50 66 db common-mode rejection ratio cmrr v dut_ = -1.5v and 6.5v, v clv_ = v chv_ = 0v (note 25) 50 55 db ac characteristics (v chv_ = v clv_ = 0v, driver terminated, unless otherwise noted) (note 4) minimum pulse width (note 31) 0.5 0.65 ns propagation delay 0.5 1 1.5 ns propagation-delay match h/l vs.l/h, individual comparator -25 +25 ps electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 21 parameter symbol conditions min typ max units change in propagation delay vs.duty cycle 500mv swing, 250mv overdrive, 2ns to23ns pulse width, relative to pw = 12.5ns -45 +45 ps propagation delay vs. common-mode voltage v swing = 200mv, 100mv overdrive, common-mode voltage = -1.4v to +6.4v(note 32) 70 ps p - p propagation-delay temperaturecoefficient 3 ps/c propagation delay vs. slew rate 1v/ns to 6v/ns, relative to 2v/ns 50 ps cdrp = 0b000 0 cable-droop compensation 1v swing, rise/fall time =500ps cdrp = 0b111 10 % driver vhh dc characteristics output-voltage range vhh 0 13 v v h h _ = 13v , i d u t _ = 10m a, v d u t _ > 12.25v +10 dc output current vhh_ = 0v, i dut_ = -10ma, v dut_ < 0.75v -10 ma current limit vhh_ = 13v, v dut_ = 0v and vhh_ = 0v, v dut_ = 13v 11 25 ma offset voltage vhh_ = 8v 30 mv gain vhh_ = 8v, 12v 0.998 1 1.002 v/v linearity relative to 8v, 12v vhh_ = 7v, 8v, 10v, 12v, 13v 10 mv linearity relative to 2v, 12v vhh_ = 0, 2v, 4v, 8v 12v, 13v 30 mv output resistance i dut_ = 2ma, vhh_ = 1v 75 output-voltage temperaturecoefficient vhh_ = 7v to 13v (note 4) 75 500 v/c ac characteristics (r l 10m , c dut_ = 100pf) vhh rise/fall times v dhv_ = 3v, vhh_ = 13v, 10% to 90% 170 ns v dhv_ = 3v to vhh_ = 13v rise 150 vhh overshoot (note 4) vhh_ = 13v to v dhv_ = 3v fall 200 mv level dacs settling time full-scale transition to within 5mv 20 s i source (vldh_), i sink (vldl_) 3.5 a vhh_, iios 2 mv differential nonlinearity all other levels 1 mv electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 22 ______________________________________________________________________________________ note 1: unless otherwise specified, all minimum and maximum specifications are production tested. all other specification testlimits are guaranteed by design. all tests are performed at nominal supply voltages and after gain and offset calibration, unless otherwise specified. note 2: guaranteed by the associated linearity test. note 3: change in offset at any voltage over the operating range. specification includes both gain and offset temperature effects.limits have been simulated over the entire operating range and verified at worst-case conditions (v dhv_ - v dlv_ > 200mv). note 4: guaranteed by design and characterization. note 5: v cc and v e e independently varied over their full range. note 6: data_ = 1v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, i out = 30ma. different values within the range of 48 to 52 are available by custom trimming (contact factory). note 7: resistance measurements are made using 2.5ma current changes in the loading instrument about the noted value.absolute value of the difference in measured resistance at the specified points, tested separately for each current polarity. note 8: rise time, unless otherwise specified for the differential inputs data_ and rcv_, is 250ps (10% to 90%) at 40mhz. (theseconditions are for bench characterization. final test conditions may differ from bench.) note 9: 8v step into ac-coupled 10 load. current supplied for a minimum of 10ns. guaranteed by design to be greater than or equal to dc drive current. note 10: v dtv_ = 1.5v, r s = 50 . external signal driven into a transmission line to produce a 0 to 3v edge at the comparator input with a 600ps rise time (10% to 90%). measurement point is at the comparator input. note 11: measured between the 90% point of the driver output (relative to its final value) and the waveform settling to within thespecified limit. note 12: propagation delays are measured from the crossing point of the differential input signals to the 50% point of expected out-put swing. note 13: average of two measurements for propagation-delay match, t lh vs. t hl . note 14: four measurements are made: dhv_ to high impedance, dlv_ to high impedance, high impedance to dhv_, and highimpedance to dlv_. the worst of the four measurements is reported. note 15: average of four measurements of propagation-delay match, drive to high impedance vs. high impedance to drive.measured from the crossing point of rcv/nrcv to the 50% point of the output waveform. note 16: average of four measurements for propagation-delay match, drive to term vs. term to drive. measured from the crossingpoint of rcv/nrcv to the 50% point of the output waveform. note 17: four measurements are made: dhv_ to dtv_, dlv_ to dtv_, dtv_ to dhv_, and dtv_ to dlv_. the worst-case differ-ence is reported. note 18: propagation-delay change is reported with respect to a 5ns pulse width. note 19: at this pulse width, the output reaches at least 95% of its nominal (dc) amplitude. the pulse width is measured at data_and ndata_. note 20: maximum data rate in transitions/second. a waveform that reaches at least 95% of its programmed amplitude may be gen-erated at half of this frequency. note 21: maximum data rate in transitions/second. a waveform that reaches at least 90% of its programmed amplitude may be gen-erated at half of this frequency. note 22: the comparators tolerate the v hh produced by the driver; however, the specifications only apply to the -1.5v to +6.5v input range. note 23: this specification is implicitly tested, by meeting the high-impedance leakage specification. note 24: change in offset at any voltage over operating range. includes both gain (cmrr) and offset temperature effects. note 25: change in offset voltage over the input range. note 26: relative to straight line between 0 and 3v. note 27: change in offset voltage with power supplies independently varied over their full range. both high and low comparatorsare tested. note 28: all propagation delays measured from v dut_ crossing calibrated chv_/clv_ threshold to crossing point of differential outputs. electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 23 note 29: all delay specifications are measured with dut_ (comparator input) as the reference. note 30: 40mhz, 0 to 1v input to comparator, reference = 0.5v, 50% duty cycle, 250ps rise/fall time, z s = 50 , driver in term mode with v dtv_ = 0v, and hysteresis disabled, unless otherwise specified. note 31: at this pulse width, the output reaches at least 90% of its nominal peak-to-peak swing. the pulse width is measured at thecrossing points of the differential outputs. 250ps rise/fall time at dut_. timing dispersion specifications are not guaran- teed. note 32: v dut_ = 200mv p-p , rise/fall time = 150ps, overdrive = 100mv, v dtv_ = v cm . valid for common-mode ranges where the signal does not exceed the operating range. specification is worst case (slowestCfastest) over the specified range. note 33: for any input slew rate up to 6v/ns, no unusual behavior should be exhibited (i.e., glitching, changing polarity, etc.). note 34: input to comparator is 40mhz at 0 to 1v, 50% duty cycle, 250ps 10% to 90% rise time. eq bandwidth = 0.22/(t tcmp ^ 2 + t tinput ^ 2 )^(1/2) where t tinput and t tcmp are the 20% to 80% transition time of the comparator input and reconstructed output. note 35: resistance measurements are made using 2.5ma current changes in the loading instrument. value reported is the absolutevalue of the difference in measured resistance over the specified range, tested separately for each current polarity. note 36: stimulus is 0 to 3v, 2.5v/ns square wave from far end of 3ns transmission line with r s = 25 , clamps set to 0 and 3v. note 37: change in offset over the entire operating range. includes both gain and offset temperature effects. note 38: interpretation of errors are expressed in terms of %fsr (percent of full-scale range) as a percentage of the end-point-to-end-point range (i.e., for the 2ma range, the full-scale range = 4ma and a 1% error = 40a). note 39: with clamps enabled, the linear dut_ current range for force voltage is defined by the clamp-current-range specification,and the linear dut_ voltage range for force current is defined by the linear fi v dut_ range specification. note 40: for currents greater than +fsr/2, v meas is greater than v iios + 4v and for currents less than -fsr/2, v meas is less than v iios - 4v. note 41: this current is supplied by the driver. note 42: v vios may be programmed to greater than 1.5v to a maximum value of 2.5v; however, the maximum valid v dut_ value must be reduced below 6.5v, as the maximum meas output is limited to 8v. because v meas_ = v dut_ + v vios , then v dut_max = 8v - v vios when v vios > 1.5v. note 43: guaranteed by driver vhh_ and dlv_ linearity tests. note 44: ivmax and ivmin do not have separate calibration registers for mi and mv modes. specifications apply with calibrationfor each mode. note 45: guaranteed by the associated accuracy test. note 46: the digital interface is compatible with 2.7v v dd 5v cmos logic. note 47: see the typical operating characteristics section. note 48: fimv settling times are a function of c dut_ and r range . increased dut_ capacitance will increase settling time. note 49: the propagation delay time is guaranteed only over the force-voltage output range. propagation delay is measured byholding v sense_ steady and transitioning ivmax_ or ivmin_. note 50: default configuration has internal 100 resistors between data and ndata, rcv and nrcv. resistor terminations from data, ndata, rcv, and nrcv to a separate pin are available by special request. note 51: at nominal supply voltages. total current for dual device. r l 10m . note 52: increasing dgs beyond 0v requires a proportional increase in the minimum supply levels. specified ranges for all dacoutput levels are defined with respect to dgs. note 53: the error of the external 2.5v reference impacts the accuracy of the dac levels; a 1% error in the 2.5v reference will trans-late to a 1% error in the dac level gain. use a precision voltage reference, such as the max6225. note 54: generate the 2.5v external reference with respect to dgs (dut ground sense). note 55: guaranteed by associated cmrr_ test. note 56: the comparator outputs are normally source side-terminated with 50 on-die to ctv_ and at the receive side of the trans- mission path. the comparator outputs are tested with the 50 on-die source resistors only with limits relative to ctv_ twice the values indicated. electrical characteristics (continued)(v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0v, v cphv_ = 7.2v, v cplv_ = -2.2v, v ctv_ = 1.4v, v bv_ = 4v, v dgs = v gnd = 0v, v chv_ = v ivmax_ = 2v, v clv_ = v ivmin_ = 1v, v com_ = 2.5v, v ldhv_ = 0v, v ldlv_ = 0v, v in_ = 2.5v, v vios = 0v, v iios = 2.5v, v clamphi_ = 5v, v clamplo_ = 0v, v hh_ = 10v, cdrp = 0b001, ro = 0b1000, hyst = 0b000, z load = 50 , t j = +70c to an accuracy of 15c, unless otherwise noted. all temperature coefficients are measured at t j = +40c to +100c, unless otherwise noted.) (note 1) downloaded from: http:///
driver time delay vs. common-mode voltage common-mode voltage (v) time delay (ps) max9979 toc04 0123456 -10 -5 0 5 10 15 20 25 rising edge falling edge normalized at v cm = 1.5v driver-to-term transition max9979 toc05 v dut_ = 0.25v/div 0 2ns/div r l = 50 to gnd, v dhv_ = 3v, v dtv_ = 1.5v, v dlv_ = 0v dhv dlv max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 24 ______________________________________________________________________________________ driver small-signal response max9979 toc01 v dut_ = 50mv/div 0 2ns/div v dlv_ = 0v r l = 50 to gnd v dhv_ = 0.5v v dhv_ = 0.2v v dhv_ = 0.1v driver large-signal response max9979 toc02 v dut_ = 0.5v/div 0 2ns/div v dlv_ = 0v r l = 50 to gnd v dhv_ = 5v v dhv_ = 3v v dhv_ = 1v driver trailing-edge timing error vs. pulse width max9979 toc03 timing error (ps) 30 -40 -30 -20 -10 0 10 20 01 02 0 2 5 15 5 pulse width (ns) normalized to pw = 5ns,period = 25ns, v dhv_ = 3v, v dlv_ = 0v positive pulse negative pulse driver to high-impedance transition max9979 toc06 v dut_ = 0.2v/div 0 2ns/div r l = 50 to gnd, v dhv_ = 1v, v dlv_ = -1v dhv dlv driver linearity error vs. output voltage v dut_ (v) linearity error (mv) max9979 toc08 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 dut_ = dlv_ typical operating characteristics (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0, v cphv_ = 7.2v, v cplv_ = -2.2v, r t = 50 || 1pf, c l = 100pf, ctv_ = 1.4v, t j = +70c, unless otherwise specified. all temperature coefficients are measured at t j = +40c to +100c.) driver linearity error vs. output voltage v dut_ (v) linearity error (mv) max9979 toc07 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 dut_ = dhv_ downloaded from: http:///
typical operating characteristics (continued) (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0, v cphv_ = 7.2v, v cplv_ = -2.2v, r t = 50 || 1pf, c l = 100pf, ctv_ = 1.4v, t j = +70c, unless otherwise specified. all temperature coefficients are measured at t j = +40c to +100c.) max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 25 driver linearity error vs. output voltage v dut_ (v) linearty error (mv) max9979 toc09 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 dut_ = dtv_ crosstalk to dut_ from dlv_ with dut_ = dhv_ v dlv_ (v) crosstalk (mv) max9979 toc10 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 normalized at v dlv_ = 0v, v dhv_ = 5v, v dtv_ = 1.5v crosstalk to dut_ from dhv_ with dut_ = dlv_ v dhv_ (v) crosstalk (mv) max9979 toc11 01234567 -0.5 0 0.5 1.0 1.5 2.0 normalized at v dhv_ = 5v, v dlv_ = 0v, v dtv_ = 1.5v crosstalk to dut_ from dtv_ with dut_ = dhv_ v dtv_ (v) crosstalk (mv) max9979 toc12 -1.5 2.5 4.5 0.5 5.5 3.5 1.5 -0.5 6.5 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 normalized at v dtv_ = 1.5v, v dlv_ = 0v, v dhv_ = 3v crosstalk to dut_ from dtv_ with dut_ = dlv_ v dtv_ (v) crosstalk (mv) max9979 toc13 -1.5 2.5 4.5 0.5 5.5 3.5 1.5 -0.5 6.5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 normalized at v dtv_ = 1.5v, v dlv_ = 0v, v dhv_ = 3v crosstalk to dut_ from dlv_ with dut_ = dtv_ v dlv_ (v) crosstalk (mv) max9979 toc14 -1.5 0 -1.0 1.0 -0.5 0.5 1.5 -0.5 0 0.5 1.0 1.5 2.0 normalized at v dlv_ = 0v, v dtv_ = 1.5v, v dhv_ = 3v crosstalk to dut_ from dhv_ with dut_ = dtv_ v dhv_ (v) crosstalk (mv) max9979 toc15 1.5 2.5 5.5 4.5 3.5 6.5 -0.5 0 0.5 1.0 1.5 2.0 normalized at v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v driver gain error vs. temperature max9979 toc16 temperature ( c) driver gain error (%) 90 80 70 60 50 -0.1 0 0.1 0.2 0.3 0.4 -0.2 40 100 dhv dlv dtv normalized at t j = +85 c downloaded from: http:///
comparator trailing-edge timing variation vs. pulse width max9979 toc21 pulse width (ns) timing variation (ps) 15 52 0 10 5 10 2015 -10 -5 0 25 30 -15 02 5 high pulse low pulse normalized at pw = 5ns,period = 25ns comparator differential output response max9979 toc23 1ns/div v out_ = 0.1v/div r l = 50 typical operating characteristics (continued) (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0, v cphv_ = 7.2v, v cplv_ = -2.2v, r t = 50 || 1pf, c l = 100pf, ctv_ = 1.4v, t j = +70c, unless otherwise specified. all temperature coefficients are measured at t j = +40c to +100c.) max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 26 ______________________________________________________________________________________ driver offset vs. temperature max9979 toc17 temperature ( c) driver offset (mv) 90 80 70 60 50 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 40 100 dhv dlv dtv normalized at t j = +85 c v dhv_ = 3.0v, v dtv_ = 1.5v, v dlv_ = 0v comparator offset vs. common-mode voltage max9979 toc18 common-mode voltage (v) comparator offset (mv) 1.5 0.5 2.5 4.5 5.5 -0.5 3.5 -1.2 -1.0 -0.6-0.8 -0.4 -0.2 0 0.2 -1.4 -1.5 6.5 clv chv normalized at v cm = 1.5v comparator rising-edge timing variation vs. common-mode voltage max9979 toc19 common-mode voltage (v) timing variation (ps) 1.5 0.5 2.5 4.5 5.5 -0.5 3.5 -4 -2 20 4 6 8 -6 -1.5 6.5 chv clv normalized at v cm = 1.5v comparator falling-edge timing variation vs. common-mode voltage max9979 toc20 common-mode voltage (v) timing variation (ps) 1.5 0.5 2.5 4.5 5.5 -0.5 3.5 10 15 2520 -5 0 5 30 35 40 -10 -1.5 6.5 clv chv normalized at v cm = 1.5v comparator timing variation vs. input slew rate max9979 toc22 slew rate (v/ns) comparator timing variation (ps) 4 25 3 0 10 20 30 -30 -20 -10 40 -40 16 v dut_ rising v dut_ falling normalized at 2v/ns comparator response to high slew-rate input max9979 toc24 3ns/div 0 300mv/div input output high-impedance mode, input = 6v/ns downloaded from: http:///
typical operating characteristics (continued) (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0, v cphv_ = 7.2v, v cplv_ = -2.2v, r t = 50 || 1pf, c l = 100pf, ctv_ = 1.4v, t j = +70c, unless otherwise specified. all temperature coefficients are measured at t j = +40c to +100c.) max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 27 comparator offset vs. temperature max9979 toc25 temperature ( c) comparator offset (mv) 50 80 60 90 70 0 0.5 1.0 1.5 -1.5 -1.0 -0.5 2.0 -2.0 40 100 normalized at t j = +70 c clamp response at source max9979 toc26 3ns/div 0 v dut_ = 0.6v/div r s = 25 , v cphv_ = 3.1v, v cplv_ = -0.1v, v source = 0 to 3v square wave active load current vs. voltage max9979 toc27 v dut_ (v) i dut_ (ma) 5.5 -0.5 1.5 3.5 4.5 0.5 2.5 0 10 15 20 -15 5 -20 -10 -5 25 -25 -1.5 6.5 v vldh_ = v vldl_ = 6v active-load linearity error i dut_ vs. v ldh_ max9979 toc28 v ldh_ (v) linearity error ( v) 1.0 -20 -10 0 10 -40 -30 20 30 40 50 -50 0.1 10.0 calibration points atv ldh_ = 300mv and 5.4v, v com_ = 6v, v ldl_ = 0v, v dut_ = -1.0v active load linearity error i dut_ vs. v ldl_ max9979 toc29 v ldl_ (v) linearity error ( v) 1 -20 -10 0 10 -40 -30 20 30 40 50 -50 0.1 10 calibration points atv ldl_ = 300mv and 5.4v, v com_ = -1v, v ldh_ = 0v, v dut_ = 6v high-impedance leakage current vs. dut_ voltage max9979 toc30 v dut_ (v) i dut_ (na) 5.5 -0.5 1.5 3.5 4.5 0.5 2.5 0 0.4 0.6 0.8 -0.6 0.2 -0.8 -0.4 -0.2 1.0 -1.0 -1.5 6.5 low-leakage current vs. dut_ voltage max9979 toc31 v dut_ (v) i dut_ (pa) 5.5 -0.5 1.5 3.5 4.5 0.5 2.5 0 10 20 30 -10-20 40 -30 -1.5 6.5 high-impedance clamp current vs. difference voltage max9979 toc32 v dut_ (v) i dut_ (ma) 5.5 -0.5 1.5 3.5 4.5 0.5 2.5 40 60 70 8010 50 0 20 30 90 -10 -1.5 6.5 v cplv_ = 5v, v cphv_ = 6.5v downloaded from: http:///
high impedance to low-leak transition max9979 toc34 10ns/div 0 20mv/div low-leak to high impedance high impedance to low-leak r load = 50 to gnd supply current (i cc vs. v cc ) max9979 toc36 v cc (v) i cc (ma) 10.3 9.9 10.1 9.7 60 80 100 120 20 40 140 0 9.5 10.5 low-leak mode t j = +70 c driver term mode, v dtv_ = 1.5v, no load typical operating characteristics (continued) (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0, v cphv_ = 7.2v, v cplv_ = -2.2v, r t = 50 || 1pf, c l = 100pf, ctv_ = 1.4v, t j = +70c, unless otherwise specified. all temperature coefficients are measured at t j = +40c to +100c.) max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 28 ______________________________________________________________________________________ high-impedance clamp current vs. difference voltage max9979 toc33 v dut_ (v) i dut_ (ma) 5.5 -0.5 1.5 3.5 4.5 0.5 2.5 -40 -20 -10 0 -70 -30-80 -60 -50 10 -90 -1.5 6.5 v cplv_ = -1.5v, v cphv_ = 0v drive to low-leak transition max9979 toc35 10ns/div 0 v dut_ = 25mv/div low-leak to drive drive to low-leak r load = 50 to gnd supply current (i ee vs. v ee ) max9979 toc37 v ee (v) i ee (ma) -5.1 -4.6 -5.0 -4.9 -4.8 -4.7 -150 -100 -50 -250 -200 0 -300 -5.2 -4.5 low-leak mode t j = +70 c driver term mode, v dtv_ = 1.5v, no load supply current (i cc vs. temperature) max9979 toc38 temperature ( c) i cc (ma) 60 80 50 90 70 60 80 100 120 20 40 140 0 40 100 driver term mode, v dtv_ = 1.5v, no load supply current (i ee vs. temperature) max9979 toc39 temperature ( c) i ee (ma) 60 80 50 90 70 -150 -100 -50 -250 -200 0 -300 40 100 driver term mode, v dtv_ = 1.5v, no load transient response fvmi range a max9979 toc40 5 s/div 0 1.5v/div v dut_ rising v meas_ rising v meas_ falling v dut_ falling v in_ = -1v to +6.5v and +6.5v to -1v r l = 200 to 2.5v downloaded from: http:///
transient response fvmi range c max9979 toc42 5 s/div 0 1.5v/div v dut_ rising v meas_ rising v meas_ falling v dut_ falling v in_ = -1.5v to +6.5v and +6.5v to -1.5v r l = 20k to 2.5v transient response fvmi range e max9979 toc44 50 s/div 0 2v/div v dut_ rising v meas_ rising v meas_ falling v dut_ falling v in_ = -1.5v to +6.5v and +6.5v to -1.5v r l = 2m to 2.5v transient response fimi range a max9979 toc45 5 s/div 0 1.5v/div v dut_ rising v meas_ rising v meas_ falling v dut_ falling v in_ = 1.1v to 4.1v and 4.1v to 1.1v r l = 200 to 2.5v, c load = 100pf transient response fimi range b max9979 toc46 5 s/div 0 1.5v/div v meas_ rising and v dut_ rising v meas_ falling and v dut_ falling v in_ = -1.5v to +6.5v and +6.5v to -1.5vr l = 2k to 2.5v, c load = 100pf typical operating characteristics (continued) (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0, v cphv_ = 7.2v, v cplv_ = -2.2v, r t = 50 || 1pf, c l = 100pf, ctv_ = 1.4v, t j = +70c, unless otherwise specified. all temperature coefficients are measured at t j = +40c to +100c.) max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 29 transient response fvmi range b max9979 toc41 5 s/div 0 1.5v/div v in_ = -1.5v to +6.5v and +6.5v to -1.5v r l = 2000 to 2.5v v dut_ rising and v meas_ rising v dut_ falling and v meas_ falling transient response fvmi range d max9979 toc43 5 s/div 0 2v/div v dut_ rising v meas_ rising v meas_ falling v dut_ falling v in_ = -1.5v to +6.5v and +6.5v to -1.5vr l = 200k to 2.5v transient response fimi range c max9979 toc47 5 s/div 0 1.5v/div v dut_ rising v meas_ rising v meas_ falling v dut_ falling v in_ = -1.5v to +6.5v and +6.5v to -1.5vr l = 20k to 2.5v, c load = 100pf transient response fimi range d max9979 toc48 12.5 s/div 0 1.5v/div v dut_ rising v meas_ rising v meas_ falling v dut_ falling v in_ = -1.5v to +6.5v and +6.5v to -1.5vr l = 200k to 2.5v, c load = 100pf downloaded from: http:///
transient response fimi range e max9979 toc49 50 s/div 0 1.5v/div v dut_ rising v meas_ rising v meas_ falling v dut_ falling v in_ = -1.5v to +6.5v and +6.5v to -1.5v r l = 2m to 2.5v, c load = 100pf transient response fimv range c max9979 toc50 5 s/div 0 1.5v/div v dut_ rising and v meas_ rising v dut_ falling and v meas_ falling v in_ = -1.5v to +6.5v and +6.5v to -1.5vr l = 20k to 2.5v, c load = 100pf typical operating characteristics (continued) (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0, v cphv_ = 7.2v, v cplv_ = -2.2v, r t = 50 || 1pf, c l = 100pf, ctv_ = 1.4v, t j = +70c, unless otherwise specified. all temperature coefficients are measured at t j = +40c to +100c.) max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 30 ______________________________________________________________________________________ transient response vhh max9979 toc51 0.1 s/div 0 2v/div driver cable-droop compensation max9979 toc52 2.5ns/div 0 v dut_ = 250mv/div r load = 50 to gnd, 3v swing,cdrp = 0b001, 0b100, 0b111 driver 1.2gbps toggle rate, 1v max9979 toc53 0.5ns/div 0 v dut_ = 80mv/div r load = 50 to gnd driver 900mbps toggle rate, 3v max9979 toc54 0.5ns/div 0 v dut_ = 200mv/div r load = 50 to gnd pmu range change b to a max9979 toc56 5 s/div 0 v dut_ = 100mv/div ac-coupled c load = 100pf, r load = 2k to 2.5v i load = -2ma, -1ma, 0, 1ma, and 2ma pmu range change a to b max9979 toc55 5 s/div 0 v dut_ = 100mv/div ac-coupled c load = 100pf, r load = 2k to 2.5v i load = -2ma, -1ma, 0, 1ma, and 2ma downloaded from: http:///
pmu mi linearity max9979 toc59 error (%fsr) 0.020 -0.020 -0.016 -0.004 0 -0.012 -0.008 0.004 0.008 0.012 0.016 -1.5 5.5 0.5 6.5 -0.5 2.5 1.5 4.5 3.5 v meas_ (v) fvmi mode, range c,v vios_ = 2.5v, v dut_ = 2.5v pmu current clamp accuracy max9979 toc62 v clamp_ (v) error (%fsr) 2.5 2.0 3.0 1.5 3.5 -0.1 0 0.1 -0.3 -0.2 0.2 0.3 0.4 -0.4 1.0 4.0 clamphi_ clamplo_ fvmi mode, range b, v iios = 2.5v typical operating characteristics (continued) (v cc = 9.75v, v ee = -4.75v, v dd = 3.3v, v hhp = 17.5v, v dhv_ = 3v, v dlv_ = 0v, v dtv_ = 1.5v, sc1 = sc0 = 0, v cphv_ = 7.2v, v cplv_ = -2.2v, r t = 50 || 1pf, c l = 100pf, ctv_ = 1.4v, t j = +70c, unless otherwise specified. all temperature coefficients are measured at t j = +40c to +100c.) max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 31 pmu fv linearity max9979 toc57 v meas_ error (mv) 4 -4 -3 -2 -1 0 1 2 3 -1.5 5.5 0.5 6.5 -0.5 2.5 1.5 4.5 3.5 v in_ (v) sense_ input, range b,i load = -2ma, 0, and 2ma pmu mv linearity max9979 toc58 error (%fsr) 0.020 -0.020 -0.016 -0.004 0 -0.012 -0.008 0.004 0.008 0.012 0.016 -1.5 5.5 0.5 6.5 -0.5 2.5 1.5 4.5 3.5 v dut _ (v) pmu mi common-mode response max9979 toc60 v in_ (v) v meas_ error (mv) 1.5 0.5 2.5 4.5 5.5 -0.5 3.5 -1 0 1 -3 -2 2 3 4 -4 -1.5 6.5 fvmi mode, range b,v iios = 2.5v, v dut_ = v in_ , normalized at v in_ = 2.5v, i load = -2ma, 0, and 2ma pmu voltage clamp accuracy max9979 toc61 v clamp_ (v) error (mv) 1.5 0.5 2.5 4.5 5.5 -0.5 3.5 -5 0 5 -15 -10 10 15 20 -20 -1.5 6.5 clamphi_ clamplo_ fimv mode downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 32 ______________________________________________________________________________________ pin description pin name description 1 meas0 channel 0 measure output 2 duthi0 channel 0 pmu high comparator output 3 dutlo0 channel 0 pmu low comparator output 4 ref dac reference input 5 dgs dut ground sense input 6, 35, 51 gnd analog ground 7 dout data output. serial-interface data output. 8 dgnd digital ground 9 cs chip-select input 10 sclk serial-clock input 11 din data input. serial-interface data input. 12 v dd digital power supply 13 load load input. serial-interface asynchronous load control. 14 rst reset input. serial-interface reset. 15 dutlo1 channel 1 pmu low comparator output 16 duthi1 channel 1 pmu high comparator output 17 meas1 channel 1 measure output 18, 37, 40, 46, 49, 68 v cc positive power supply 19, 36, 39, 47, 50, 67 v ee negative power supply 20 hizmeasp1 channel 1 high-impedance enable input for pmu measure output 21 lleakp1 channel 1 low-leak enable input 22 nrcv1 channel 1 negative receive multiplexer control input 23 rcv1 channel 1 positive receive multiplexer control input 24 bv1 channel 1 bias voltage input 25 ndata1 channel 1 negative data multiplexer control input 26 data1 channel 1 positive data multiplexer control input 27 envhhp1 channel 1 high-voltage mode enable input 28 ncl1 channel 1 negative low comparator output 29 cl1 channel 1 positive low comparator output 30 ctv1 channel 1 comparator termination voltage 31 nch1 channel 1 negative high comparator output 32 ch1 channel 1 positive high comparator output 33 sense1 channel 1 pmu sense input 34, 42, 52 n.c. no connection. not internally connected. 38 dut1 channel 1 dut connection downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 33 pin description (continued) pin name description 41 temp temperature output 43 v hhp high-voltage power supply 44 pmu-f pmu external force connection 45 pmu-s pmu external sense connection 48 dut0 channel 0 dut connection 53 sense0 channel 0 pmu sense input 54 ch0 channel 0 positive high comparator output 55 nch0 channel 0 negative high comparator output 56 ctv0 channel 0 comparator termination voltage 57 cl0 channel 0 positive low comparator output 58 ncl0 channel 0 negative low comparator output 59 envhhp0 channel 0 high-voltage mode enable input 60 data0 channel 0 positive data multiplexer control input 61 ndata0 channel 0 negative data multiplexer control input 62 bv0 channel 0 bias voltage input 63 rcv0 channel 0 positive receive multiplexer control input 64 nrcv0 channel 0 negative receive multiplexer control input 65 lleakp0 channel 0 low-leak enable input 66 hizmeasp0 channel 0 high-impedance enable input for pmu measure output e p exposed pad. internally connected to ground. connect to a large open copper pcb plane or heatsinkto maximize thermal performance. not intended as an electrical connection point. detailed description the max9979 dual-channel pin electronics dcl/pmuintegrates multiple pin-electronics functions into a sin- gle ic. each channel includes a four-level pin driver, a window comparator, a differential comparator, dynamic clamps, a versatile pmu, an active load, and 14 inde- pendent 16-bit level-setting dacs. additionally, each channel of the max9979 features programmable cable- droop compensation for the driver output and for the comparator input, adjustable driver output resistance, and driver slew-rate adjustment. the max9979 driver features a wide -1.5v to +6.5v high- speed operating range, high-impedance and active-ter- mination (3rd-level drive) modes, and is highly linear even at low voltage swings. the max9979 also features a built-in super voltage (vhh) level up to 13v. the driver provides high-speed differential control inputs compati- ble with most high-speed logic families. the window comparators provide extremely low timing variation overchanges in slew rate, pulse width, or overdrive voltage, and have 50 source outputs internally terminated to an applied voltage at ctv_. when high-impedance mode isselected, the programmable dynamic clamps provide damping of high-speed dut waveforms. the 20ma active load facilitates fast contact testing when used in conjunction with the comparators, and functions as a pullup for open-drain/collector dut outputs. the pmu offers five current ranges from 2a to 50ma and can force and measure current or voltage. placing the max9979 dut_ output into its very low-leakage state disables the dcl functions and the pmu force function. this feature is convenient for making iddq measure- ments without the need for an output disconnect relay. low-leakage control is independent for each channel. an spi-compatible serial interface and external inputs configure the max9979. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 34 ______________________________________________________________________________________ 20 r out control 25 ? 2.5 load control dhv dtv dlv vhh* iios vldl ivmax* vin pmu mux/driver vcom cphv dac key: clamphi* clamplo ivmin* droop compensation comparators active load to other channel droop compensation dut from other channel slew control serial interface input select hysteresis control serial bits high-impedance control hizmeasp_ *shared levels. dutlo_ duthi_ range control 4x vios sense_ dgs dut_pmu-f pmu-s 1x meas_ temp_ envhhp_ dgnd gnd v hhp v ee v dd v cc bv_ ref nrcv_ rcv_ ndata_ data_ ch_ nch_ ctv_ cl_ ncl_ 10k cplv clamps vldh rst load lleakp_ din sclk cs chv* clv* max9979 figure 1. simplified block diagram. only one of two channels is shown. the pmu is shown in high range. the single serial interface controls both channels. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 35 the integration of dcl and pmu functions in themax9979 requires defined states to manage the inter- action of these resources. the pmu controls supersede those of the dcl, as described below and shown in table 1. important details to keep in mind are: ? normal high-speed dcl operation is intended only when the pmu is in the fnmn state and the dcl isavailable, as indicated by note b in table 1. ? forcing lleakp_ = 0 immediately places the dcl into low-leak mode, and the pmu into its high-impedance state independent of any other pro- grammed control bit or external control inputs. forcing lleakp_ = 1 is required to allow any other mode of operation. ? forcing hizforce_ = 1 enables the pmu and simultaneously forces the dcl into low-leak mode. ? additional pmu settings such as the force and mea- sure modes, current range, the measure output,comparators, and the clamp features are controlled as described later in this document. ? the max9979 provides calibration modes under which both the dcl and the pmu are simultaneouslyactive. forcing hizforce_ = 0 ordinarily disables the pmu, however, when lleaks_ is not asserted,the fmode_ and mmode_ bits select these calibra- tion modes. while in a calibration mode, the dclstates are still selected by the controls normally associated with those functions. when in a calibra- tion mode, the pmu range a is not available. the pmu range defaults to range b if the serial-interface bit rs2_ = 1. driver the driver uses a high-speed multiplexer to select oneof three dac voltages (dhv_, dlv_, and dtv_), or to select high-impedance mode. multiplexer switching is controlled by high-speed differential inputs data_/ndata_ and rcv_/nrcv_ and mode-control bit tmsel_ (see table 2). the multiplexer output is buffered to drive dut_. a programmable slew-rate cir- cuit controls the slew rate of the buffer input. in high-impedance mode, the clamps and comparators remain connected to dut_, the dut_ bias current is less than 2a, and the node continues to track high- speed signals. in low-leakage mode, the bias current at dut_ is further reduced to less than 10na, yet signal tracking slows. the nominal driver output resistance is 50 and fea- tures an adjustment range of 2.5 through the serial interface in 360m increments. contact the factory for different output resistance values. table 1. max9979 mode selection modes driver comparator load pmu fmode_ mmode_ lleakp_ hizforce_ note low leak low leak low leak fvmi 0 0 1 1 low leak low leak low leak fvmv 0 1 1 1 low leak low leak low leak fimi 1 0 1 1 pmu low leak low leak low leak fimv 1 1 1 1 low leak available available fvmi 0 0 1 0 a available available available fimv 0 1 1 0 a available available available fnmn 1 0 1 0 b dcl available available available fnmv 1 1 1 0 a low leak low leak low leak fnmn x 0 0 x fnmx low leak low leak low leak fnmv x 1 0 x a = calibration modes. b = normal high-speed dcl operation mode. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 36 ______________________________________________________________________________________ driver slew control a slew-rate circuit controls the slew rate of the bufferinput. select one of four possible slew rates according to table 3. the speed of the internal multiplexer sets the 100% driver slew rate (see the driver large-signal response graph in the typical operating characteristics section). sc1 and sc0 are set to 0 at power-up or when rst is forced low. vhh function vhh allows dut_ to drive voltages up to 13v. thevhh_ dac, which doubles as the pmus clamphi_ dac, adjusts from 0 to +13v. table 2 indicates the control settings required to set dut_ to vhh_. table 23 shows the transfer function for the vhh_ dac. driver cable-droop compensation the driver incorporates active cable-droop compensa-tion. at high frequencies, transmission-line effects from the dut_ output, across the tester signal delivery path to the device under test, can degrade the output wave- form fidelity, resulting in a highly degraded or unusable signal. the compensation circuit counters this degrada- tion by adding a double time-constant decaying wave- form to the nominal output waveform (pre-emphasis).figure 2 depicts a comparison between a typical driver and the max9979, and shows how droop compensa- tion counters signal degradation. control bits cdrp0, cdrp1, and cdrp2 vary the amplitude of the compen- sation signal. table 4 shows the percent compensation as a function of control bit settings. the power-on-reset and rst values for cdrp0, cdrp1, and cdrp2 are 0. the specified default value is cdrp0 = 1 for electrical characteristics table data. table 2. driver control serial-interface bits digital inputs lleaks_ envhhs_ tmsel_ lleakp_ envhhp_ rcv_ data_ driver output 0 x* x 1 1 0 0 drive to dlv 0 x* x 1 1 0 1 drive to dhv 000111x high-impedance receive 001111x drive to dtv 0 1 x 1 x 1 x drive to vhh** 0 0 x 1 0 x x drive to vhh** x x x 0 x x x low leak 1xxxxxx low leak * specified dhv, dlv transition times are not altered by the state of envhhs_. ** pmu and active load must be disabled to drive to vhh_ ( hizforce_ = 0, fmode_ = 1, mmode_ = 0, lddis_ = 1). table 3. driver slew control sc1_ sc0_ driver slew rate (%) 0 0 100* 01 7 5 10 5 0 11 2 5 * the power-on-reset and rst default value. typical driver dut transmission loss transmission loss dut mux waveform shaping buffer cdrp_ max9979 figure 2. cable-droop compensation downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 37 adjustable driver output impedance ( r o ) the max9979s nominal 50 driver output resistance is adjustable by 2.5 with a 360m resolution. the ro bits in the dcl calibration register set the resistance value. table 5 presents the output resistance controllogic. the output resistance is set to r o + 0.0 (0b1000) at power-up or when rst is forced low. table 4. cable-droop compensation control serial-interface bits cdrp2_ cdrp1_ cdrp0_ d r oo p co m pen sa tio n ( % ) 000 0 * 0 0 1 1.5** 010 3 0 1 1 4.5 100 6 1 0 1 7.5 110 9 1 1 1 10.5 * the power-on-reset and rst default value. ** specified default value for electrical characteristics table data. table 5. output resistance control serial-interface bits ro3_ ro2_ ro1_ ro0_ driver output resistance ( ) 0000 r o - 2.88 0001 r o - 2.52 0010 r o -2.16 0011 r o - 1.80 0100 r o - 1.44 0101 r o - 1.08 0110 r o - 0.72 0111 r o - 0.36 1000 r o + 0* 1001 r o + 0.36 1010 r o + 0.72 1011 r o + 1.08 1100 r o + 1.44 1101 r o + 1.80 1110 r o + 2.16 1111 r o + 2.52 * power-on-reset and rst default value. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 38 ______________________________________________________________________________________ driver data invert mode the data_/ndata_ signals for a driver channel areinternally inverted when the invert_ bit in the dcl reg- ister is asserted. the invert_ bit is set to 0 at power- up or when rst is forced low. driver differential data mode the max9979 allows the drivers to be configured forcontrol of both channels from the channel 0 data0/ndata0 inputs. this feature allows the two channels to drive dut nodes in parallel, providing a 25 driver at twice the nominal drive current. enable this feature by setting the differential0 bit in thedcl register. the differential0 bit is set to 0 at power-up or when rst is forced low. driver invert + differential data mode combining the differential and the invert modes allowsthe two channels to produce complementary outputs at dut0 and dut1 from a single digital data stream at data0/ndata0. the driver block diagram (figure 3) shows the logic of the differential and inverted modes. bias voltage input (bv_) apply a voltage to bv_ that is the v ih voltage used for the data_ and rcv_ inputs (v ih (data_, rcv_)) < v bv < 3.5v, because there are esd-protection diodes between bv_ and the high-speed inputs. failure to dothis turns on the protection diodes, degrading the data_ and rcv_ signals. input bias current for bv_ is less than 1a. driver voltage clamps the voltage clamps (high and low) limit the voltage atdut_ and suppress reflections when the channel is configured as a high-impedance receiver. the clamps behave as diodes connected to the outputs of high- current buffers (figure 1). internal circuitry compen- sates for the diode drop at 1ma clamp current. set the clamp voltages using the level-setting dacs (cphv_ and cplv_). the clamps are enabled only when the driver is in the high-impedance mode. for transient suppression, set the clamp voltages to approximately the minimum and maximum expected dut_ voltage range. the optimal clamp voltages are application-spe- cific and must be empirically determined. set the clamp voltages at least 0.7v outside the expected dut_ volt-age range when not using the clamps. overvoltage protection then remains active without loading dut_. driver clamps are always and only enabled in driver high-impedance mode. high-speed comparators the max9979 provides two independent high-speedcomparators for each channel. each comparator has one input connected internally to dut_ and the other input connected to either chv_ or clv_ (figure 4). cable-droop compensation is present on both chan- nels. comparator outputs are a logical result of the input conditions. this configuration switches a 16ma current source between the two outputs, and each output has an internal termination resistor connected to ctv_. these resistors are typically 50 . use alternate configurations to termi- nate different path impedance provided that the absolutemaximum ratings are not exceeded. note that the resistor value also sets the voltage swing. the output provides a nominal 400mv p-p swing with a 50 load termination, and a 50 source termination. see the electrical characteristics section titled high-speed comparators, logic outputs for definition of the v oh voltage. single-ended window comparator set the differential1 bit = 0 in the channel 1 dclregister to enable the high-speed window comparator. dac voltages chv_ and clv_ control the comparator thresholds. table 6 shows the truth table for the com- parators. figure 4 shows the comparator block dia- gram. table 6. single-ended windowcomparator truth table condition ch_ cl_ v dut_ < v chv_ v dut_ < v clv_ 00 v dut_ < v chv_ v dut_ > v clv_ 01 v dut_ > v chv_ v dut_ < v clv_ 10 v dut_ > v chv_ v dut_ > v clv_ 11 downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 39 max9979 output buffer vhhenable 20 100 ro0 25 ? 2.5 cdrp0 droop control slew control tmsel0 lleaks0 lleakp0 nrcv0 bv0* rcv0 envhhp0 envhhs0 invert0 invert1 differential0 sc0 mux 0 cplv0 vhh0 dut0dgs dut1 dlv0 dtv0 dhv0 cphv0 cable compensation 100 ndata0 data0 100 data1 ndata1 output buffer vhhenable 20 100 ro1 25 ? 2.5 cdrp1 droop control slew control tmsel1 *see the bias voltage input (bv_) section . lleaks1 lleakp1 nrcv1 bv1* rcv1 envhhp1 envhhs1 sc1 mux cplv1 vhh1 dlv1 dtv1 dhv1 cphv1 cable compensation 1 0 1 0 figure 3. driver block diagram downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 40 ______________________________________________________________________________________ chv0 clv0 1 0 1 0 max9979 cdrp0 dut0 dgs lleakp0 hyst0 cable-droop compensation channel zero comparators differential comparators ch0 nch0 ctv0 cl0 ncl0 lleaks0 chv1 clv1 0 1 0 1 cdrp1 dut1lleakp1 hyst1 cable-droop compensation channel one comparators ch1 50 x 4 50 x 4 nch1 ctv1 cl1 ncl1 lleaks1 differential1 1 1 figure 4. high-speed comparators block diagram downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 41 differential window comparator set the differential1 bit = 1 in the channel 1 dclregister to enable the high-speed differential window comparator. chv1 and clv1 control the differential comparator thresholds. chv0 and clv0 are not used when differential comparison is active. the valid volt- age range for chv1 and clv1 in differential compari- son mode is 1v. setting levels outside 1v does not damage the device, but performance is not guaran- teed. differential comparator outputs are multiplexed to the channel 0 comparator outputs. the channel 1 com- parator outputs are both forced to a high state. figure 4 shows the operation of the comparators. table 7 shows the truth table for the differential comparator. figure 4 shows the comparator block diagram. comparator hysteresis the dcl calibration register controls the high-speedcomparator hysteresis. the hyst bits of that register select one of eight values (0, 2mv, 4mv, 6mv, 8mv,10mv, 12mv, or 15mv). hysteresis control affects both single-ended and differential comparators. the hyst bits are set to 0b000 at power-up or when rst is forced low. table 8 shows the hyst bit functions. vcom_ lleakp_ dut_ lldis_ ldcal_ tmsel_ lleak_ rcv_ nrcv_ dgs 0 max9979 vldh_ vldl_ 100 trm figure 5. active load block diagram (one channel shown) table 7. differential window comparator truth table table 8. hysteresis logic condition ch0 cl0 v dut0 - v dut1 < v chv1 - v dgs v dut0 - v dut1 < v clv1 - v dgs 00 v dut0 - v dut1 < v chv1 - v dgs v dut0 - v dut1 > v clv1 - v dgs 01 v dut0 - v dut1 > v chv1 - v dgs v dut0 - v dut1 < v clv1 - v dgs 10 v dut0 - v dut1 > v chv1 - v dgs v dut0 - v dut1 > v clv1 - v dgs 11 serial-interface bits hyst1_ hyst1_ hyst0_ comparator hysteresis (mv) 000 0 001 2 010 4 011 6 100 8 101 1 0 110 1 2 111 1 5 downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 42 ______________________________________________________________________________________ comparator cable-droop compensation control comparator cable-droop compensation usingthe same serial bits used for the driver droop compen- sation, cdrp_. cable-droop compensation is active for both the single-ended and the differential comparators. active load the active load is a linearly programmable currentsource and sink, a commutation buffer, and a diode bridge (figure 5). level-setting dacs vldh_ and vldl_ set the sink and source currents from 0 to 20ma. level-setting dac vcom_ sets the commutation buffer output voltage. the source and sink naming convention is referenced to the max9979, so current out of the max9979 constitutes source current and current into the max9979 constitutes sink current. the programmed source current loads the device under test when v dut _ < v com _. the programmed sink current loads the device under test when v dut _ > v com _. the high-speed differential inputs (rcv_/nrcv_) and three bits of the control word(lldis_, ldcal_, and tmsel_) control the load. lleakp_ and lleak_ place the load into low-leakage mode. the low-leakage controls override other controls. table 9 details load control logic. load calibration enable (ldcal_) ldcal_ allows the load and driver to be simultaneouslyenabled for diagnostic purposes. lddis_ overrides ldcal_. parametric measurement unit (pmu) the max9979 pmu forces and measures voltages from-1.5v to 6.5v, and currents up to 50ma. the lowest full-scale current range is 2a. available pmu modes are force-voltage/measure voltage (fvmv), force-volt- age/measure current (fvmi), force-current/measure current (fimi), force-current/measure voltage (fimv), force-nothing/measure voltage (fnmv), and force-noth- ing/measure nothing (fnmn). figure 6 presents a block diagram on the pmu. pmu current-range selection three bits from the control word (rs0, rs1, and rs2)control the full-scale current range for both force- current (fi) and measure-current (mi) modes. the pmu ranges are independent of the programmed pmu mode, except range a, which is not allowed in any cali- bration mode. in these modes range a defaults to range b (see table 1). table 10 presents the pmu cur- rent-range control logic. table 9. load control logic rcv_ tmsel_ lddis_ ldcal_ lleaks_ lleakp_ load state xxxx1x low leak xxxxx0 low leak 0x0001o f f x x 1 x 0 1 off 110001o f f 100001o n xx0101o n table 10. pmu current-range control digital input serial-interface bits lleakp_ hizforce_ rs2_ rs1_ rs0_ range xx000 e xx001 d xx010 c xx011 b x01xx b * 011xx b * 111xx a * range a operation is not allowed for pmu high-impedance modespmu defaults to range b. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 43 iios to other channel measi to otherchannel measv dutlo_ 4x vios vin_ 1x pmusense_ sense_ dgs dut_ pmu-s pmu-f 1 0 1 0 1 0 1 1 0 1 0 mmode_ fmode_ ref hysten_ disable_ ivmax_ ivmin_ clamplo_ clamphi_ clenable_ duthi_ hizmeasp_ meas_ clamp control hizmeass_ 25 range-setting resistors 1 hizforce_ lleakp_ pmu-s_ 1 pmu-f_ 100 2.5k 10k to other channel max9979 figure 6. pmu block diagram (one channel shown) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 44 ______________________________________________________________________________________ pmu comparators two comparators, configured as a window comparator,monitor the measv_ and measi_ signals (figure 6). level-setting dacs ivmax_ and ivmin_ set the high and low thresholds that determine the window (dac ivmax_ shares duties with vhh_). both pmu window comparator outputs are open-drain and share a single serial disable bit ( disable_ ) that puts the outputs in a high-impedance, low-leakage state. meas_ includes theinfluence of vios, while the comparator outputs do not. table 11 presents the pmu comparator output logic. pmu measure output (meas_) the meas_ output presents a voltage proportional tothe measured voltage or current. force logic input hizmeasp_ or bit hizmeass_ low to place meas_ in a low-leakage, high-impedance state. vios offset level for pmu measure voltage meas_ output in mv mode, use the vios level-setting dac to offsetthe meas_ output voltage. the valid range of vios is 0 to 1.5v, but the vios dac is programmable from -1.25v to +3.75v. the single vios dac is shared by both channels. vios allows level shifting the meas_ output, useful when meas_ is read by a unipolar adc. the nominal 0x0000 to 0xffff code range for vios equates to -1.25v to +3.75v. the power-on-reset and rst state of vios is 0x4000, or 0v, the level for normal operation. the meas_ output tracks dgs. the viosdac range is programmable outside the valid opera- tional range of the vios signal, but doing so will not harm the device. table 23 presents the vios dac transfer function. iios reference level for pmu measure current meas_ output in mi mode, adjust the meas_ output around the i dut_ = 0 center reference using the iios level-setting dac.iios is programmable from 0 to 5v, but levels outside of the 2v to 4v range are invalid. the single iios dac is shared by both channels. iios allows level shifting the 4v mi output range to fully above ground at the meas_ output, useful when meas_ is read by a unipo- lar adc. the nominal 0x0000 to 0xffff code range for iios equates to 0 to 5v. the power-on-reset and rst state of iios is 0x4000, or 1.25v. for normal operation,the level of iios is 2.5v for a -1.5v to +6.5v mi meas_ output. the iios dac range is programmable outside the valid operational range of the iios signal, but doing so will not harm the device. table 23 presents the iios dac transfer function. the mi meas_ output is a buffered version of an inter- nal node that is used to close the force-current loop. the sourcing range of forced current is limited for iios levels above 3.5v by the v in upper limit of approxi- mately 7.5v. pmu sense control bit pmusense_ determines which of two inputsreaches the pmu sense amplifier (figure 6). one input is from dut_ through an internal 10k resistor, the other input is from external input sense_. not shown infigure 6 is a third input to the sense amplifier (gnd), which is used in vhh and fnmn modes to isolate and protect the amplifier from potential overvoltage and glitches. gnd is connected automatically based on mode setting and no discrete control is required. table 12 presents the pmu sense control logic. table 11. pmu comparator output logic comparator outputs disable_ bit condition duthi_ dutlo_ 0 x high impedance high impedance 1v measure > v ivmax and v ivmin 01 1v ivmax > v measure > v ivmin 11 1v ivmax and v ivmin > v measure 10 1v ivmin > v measure > v ivmax *0 0 * normal operation is with v ivmax > v ivmin . this condition has v ivmin > v ivmax . this does not cause any problems with the operation of the comparators. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 45 pmu analog signal polarities in fv mode, dut_ voltage is proportional to level-setting dac voltage v in_ . in fi mode, the current flow- ing out of dut_ is equal to:positive current is defined as flowing out of the pmu. in fn mode, the pmu output is high impedance. table 13 presents the range resistor values. table 23 presents the dac transfer functions. pmu voltage clamps voltage clamps are available on the pmu output only inthe fi mode. program the clamps with level-setting dacs clamplo_ and clamphi_. the pmu voltage clamps handle the full 50ma and are triggered by the voltage at dut_ independent of the voltage at sense_. the voltage clamps override the pmu only, and do not limit the voltage of external sources. if an external source drives dut_ beyond a voltage clamp level, thepmu will current limit safely. when a pmu voltage clamp is active and at its limit, the mv and mi functions remain valid. do not let external voltage levels at dut_ exceed the absolute maximum rating limits. pmu current clamps current clamps are available on the pmu output only inthe fv mode. program the clamps with level-setting dacs clamplo_ and clamphi_. the pmu current clamps handle the full current range (50ma for range a, 2ma for range b, etc.). if the clamp currents are exceeded, the pmu enters a constant-voltage mode. the current clamp circuits override the pmu only, and do not limit external sources. when a pmu current clamp is active, the mv and mi functions are still valid. pmu clamp enable the clenable_ bit in the pmu register enable the volt-age and current clamps. table 14 presents the clamp enable control logic. vv r in iios range () 4 table 12. pmu sense control logic digital input serial-interface bits lleakp_ hizforce_ fmode_ mmode_ pmusense_ pmu mode sense path 1 1 x x 0 fymy* internal 1 1 x x 1 fymy* external 1 0 0 x 0 fvmy* (calibration) internal 1 0 0 x 1 fvmy* (calibration) external 1 0 1 0 x fnmn gnd 1 0 1 1 0 fnmv (calibration) internal 1 0 1 1 1 fnmv (calibration) external 0 x x 0 x fnmn gnd 0 x x 1 0 fnmv (calibration) internal 0 x x 1 1 fnmv (calibration) external table 13. range resistor values range resistor value ( ) a2 0 b 500 c5 k d 50k e 500k table 14. clamp enable control logic clenable_ bit mode 1 clamps enabled 0 clamps disabled * y = v or i. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 46 ______________________________________________________________________________________ pmu voltage/current-limit flags the pmu features two comparators, arranged as a win-dow comparator, to flag current or voltage levels, allow- ing fast go/no-go testing. the comparators monitor the load current or voltage, and compare it to level-setting dacs ivmax and ivmin. the mmode_ bit selects whether the window comparator monitors measv_ or measi_ (figure 6). if mmode_ selects measv_ then the pmusense_ bit selects either the sense_ input or dut_ (figure 6). independent control of pmu feedback switch and measure switch two single-pole/double-throw (spdt) switches deter-mine the mode of operation of the pmu. one switch determines whether the sensed dut_ current or dut_ voltage is fed back to the input, and thus determines which of these parameters is forced. the other switch determines whether the sensed dut_ current or dut_ voltage is presented at meas_. independent control of these switches and the force high-impedance state allow for flexible modes of operation beyond the tradi- tional force-voltage/measure-current (fvmi) and force- current/measure-voltage (fimv) modes. the modes supported are: ? fvmi: force-voltage/measure-current mode ? fimv: force-current/measure-voltage mode ? fvmv: force-voltage/measure-voltage mode ? fimi: force-current/measure-current mode ? fnmv: force-nothing/measure-voltage mode ? fnmn: force-nothing/measure-nothing mode pmu measure output high-impedance control the meas_ output features a low-leakage, high-imped-ance state. to activate this state, either place the hizmeass_ bit low or force the hizmeasp_ logic input low. the two controls are logically anded together(figure 6). the hizmeasp_ input allows multiplexing between pmu measure outputs without the use of the ser-ial interface. at power-up, hizmeass_ defaults low, plac- ing meas_ in a high-impedance state. table 15 presentsthe high-impedance control logic for the meas_ output. pmu low-leakage mode the pmu output features a low-leakage, high-imped-ance state. to activate this state, either place the hizforce_ bit low or force the lleakp_ logic input low. the two controls are logically anded together(figure 6). at power-up, hizforce_ defaults low, placing the pmu in a low-leakage state. table 1 presents thelow-leakage logic for the pmu output. pmu dut ground sense (dgs) all the dac and meas_ outputs track with respect tothe dut ground sense input (dgs). connect dgs to the ground of the device under test. pmu dut_ node force and sense switches the max9979 features additional pmu force (pmu-f)and pmu sense (pmu-s) connections, through serial- controlled switches, that are shared between channels (figure 6) and can be used to connect an external pmu. the force switch is maximum 100 , and the sense switch is maximum 2.5k . pmu dut_ voltage swing vs. dut_ current and power-supply voltages two issues limit the dut_ voltage that the pmu delivers.the first issue is the headroom required by the ampli- fiers and other on-chip circuitry at zero output current. the second issue is the headroom required with sense resistor and additional circuit voltage drops at full-scale current. when the pmu is sourcing or sinking dut_ cur- rent, the voltage range is reduced linearly. this compli- ance curve applies to both fv and fi modes and is independent of v dgs . because the forced dut_ voltage in fv mode is = dgs + v in , v dut_ is further limited by the v dgs and the -2.5v to +7.5v v in range. force out- put capabilities of the pmu are presented in figure 7.these limitations are based on the guaranteed perfor- mance of the max9979. operating the dut node outside these limits will not harm the max9979, as long as the absolute maximum rating limits are observed. with the above considerations, it is possible to extend the range of the dut swing beyond the limits of figure 7. however, some specifications, such as linearity, will begin to degrade. performance while operating outside the limits shown in figure 7 is not guaranteed. table 15. measure output high-impedancecontrol logic hizmeass_ bit hizmeasp_ input meas_ state 1 1 measure output enabled 1 0 high impedance 0 1 high impedance 0 0 high impedance downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 47 serial interface an spi-compatible serial interface and the logic-con-trolled inputs shown in table 1 control the max9979. the serial interface, detailed in figure 8, operates with clock speeds up to 50mhz and includes the signals cs , sclk, din, rst , load , and dout. serial-interface tim- ing is shown in figure 9 and timing specifications aredetailed in the electrical characteristics section. loading data into the max9979 load data into the 24-bit shift register from din on therising edge of sclk, while cs is low (figure 8). the max9979 is updated when the control and level-settingdata are latched into the control and level-setting regis- ters. the control and level-setting registers are separated from the shift register by the input and channel-select registers. two methods allow data to transfer from the shift register to the control and level-setting registers, depending on the state of external digital input load . holding load high during the rising edge of cs allows the shift register data to transfer only into the input andchannel-select registers. force load low to transfer the data into the control and level-setting registers.changes update on the falling edge of load , which allows preloading of data and facilitates synchronizingupdates across multiple devices. i dut_ v dut +fsr/2 -fsr/2 -1.1v (b?) 4.5v (a) 6.5v-1.5v 6.1v (b?) 1.1v (a) figure 7. output-voltage range max9979 cs sclk din load rst dout d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 shift register channel-select register input registers 16 8 pmu control register dcl control register level-setting dacs and dac calibration registers figure 8. serial-interface block diagram downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 48 ______________________________________________________________________________________ holding load low during the rising edge of cs forces the input and channel-select registers to become trans-parent and all data transfers through these registers directly to the control and level-setting registers. changes update on the rising edge of cs . figures 10 and 11 show how load and cs function, and also the data configuration of sclk, din, and dout.the calibration registers change on the rising edge of cs , regardless of the state of load . dout dout is a buffered version of the last bit in the serial-interface shift register. the complete contents of the shift register can be read at dout during the next write cycle. to shift data out without modifying any registers, perform a write with address bits a4 and a5 set to 0. use dout to daisy chain multiple devices, and/or to verify that data were properly shifted in during the pre-vious communication. controlling the max9979 control and level-setting registers are selected toreceive data based on the channel and mode-select bits (a0Ca7). table 16 presents the control register bits and their functions. level-setting dac data and control- register data are contained in the 16 data bits d0Cd16. tables 15, 16, and 17 detail the bit functions. clock in bit a7 first, and bit d0 last, as shown in figure 8. bit a6 allows access to the dac calibration registers. use the calibration registers to adjust the gain and off- set of each dac. set bit a6 to write to the calibration registers (table 18). see the level-setting dacs sec- tion for more information. sclk cs din a7 a6 a5 a4 a3 a2 d1 d0 t ch t cl t dh t ds t csho t css1 t csh1 t cswh a7 last t do t cll dout load t csso a6 last a5 last a4 last a3 last a2 last d1 last d0 last a7 rst t rst t cshld figure 9. serial-interface timing downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 49 cs sclk din input and channel registers updated dout load level-setting and control registers updated a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d3 d2 d1 d0 a7' a6' a5' a4' a3' a2' a1' a0' d15' d14' d3' d2' d1' d0' a7 first bit from previous write last bit from previous write 01 23 45 6789 20212223 rst figure 10. using load to update the level-setting and control registers cs sclk din dout load = 0 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d3 d2 d1 d0 a7' a6' a5' a4' a3' a2' a1' a0' d15' d14' d3' d2' d1' d0' a7 01 23 45 6789 20212223 rst first bit from previous write last bit from previous write input, channel, level-setting and control registers all updated figure 11. using cs to update the level-setting and control registers ( load held low) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 50 ______________________________________________________________________________________ table 16. max9979 control and calibration register bits register function cdrp_ driver and comparator cable-droop compensation clenable_ pmu clamp enable differential0 select data1/ndata1 as data control for both channels 1 and 2 (figure 3) differential1 enable differential comparator outputs (figure 4) disable_ pmu comparator output disable envhhs_ vhh_ mode enable fmode_ pmu force-mode control gcal_ dac gain calibration hizforce_ pmu dut_ high-impedance control hizmeass_ pmu measure output high-impedance control hyst_ high-speed comparator hysteresis select hysten_ pmu comparator hysteresis enable invert_ data_/ndata_ polarity control ldcal_ load calibration enable lddis_ load disable lleaks_ dcl low-leak enable mmode_ pmu measure-mode control ocal_ dac offset calibration pmu-f_ force switch enable (figure 6) pmu-s_ sense switch enable (figure 6) pmusense_ pmu measv input control ro_ driver output resistance select rs_ pmu current range select sc_ driver slew-rate control tmsel_ driver terminate select control tmux_ factory use only. program to 0. table 17. serial-input data overview bit function a7 not used. write 0 or 1 a6 calibration register write enable a5 channel 1 write enable a4 channel 0 write enable a3Ca0 register address (see table 18) d15Cd0 register data (see table 19) downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 51 table 18. register address bits bits register a3 a2 a1 a0 a6 = 0 a6 = 1 0 0 0 0 dcl control dcl calibration 0 0 0 1 dhv level dhv calibration 0 0 1 0 dlv level dlv calibration 0 0 1 1 dtv level dtv calibration 0 1 0 0 chv level/pmu ivmax chv calibration 0 1 0 1 clv level/pmu ivmin clv calibration 0 1 1 0 cphv level cphv calibration 0 1 1 1 cplv level cplv calibration 1 0 0 0 pmu control 1 0 0 1 vin level vin calibration 1 0 1 0 vcom level vcom calibration 1 0 1 1 vldh level vldh calibration 1 1 0 0 vldl level vldl calibration 1 1 0 1 vios/iios* level vios/iios* calibration 1 1 1 0 clamphi/vhh level clamphi/vhh calibration 1 1 1 1 clamplo level clamplo calibration table 19. data bit assignments* dac gain and offset calibration registers bit dcl control register** dcl calibration register** pmu control register** level-setter register vin all others d0 sc0 ro0 fmode_ bit 0 (lsb) ocal0 ocal0 d1 sc1 ro1 mmode_ bit 1 ocal1 ocal1 d2 lleaks ro2 rs0_ bit 2 ocal2 ocal2 d3 tmsel ro3 rs1_ bit 3 ocal3 ocal3 d4 lddis hyst0 rs2_ bit 4 ocal4 ocal4 d5 invert hyst1 clenable_ bit 5 ocal5 ocal5 d6 differential hyst2 hizforce_ bit 6 ocal6 ocal6 d7 ldcal cdrp0 hizmeass_ bit 7 ocal7 ocal7 d8 envhhs cdrp1 disable_ bit 8 gcal0 gcal0 d9 tmux0 = 0 cdrp2 pmusense_ bit 9 gcal1 gcal1 d10 tmux1 = 0 hysten_ bit 10 gcal2 gcal2 * channel 0 register programs the vios level; channel 1 register programs the iios level. select channels with bits a4 and a5. *the data bits enter the shift register in the order, msb to lsb. **the dcl control, dcl calibration, and pmu control registers default to 0x0004, 0x0008, and 0x0003 respectively at power-up. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 52 ______________________________________________________________________________________ level-setting dacs the max9979 includes 28 level-setting dacs that pro-vide the dc voltage levels for the various control and monitor circuits of the 2-channel max9979. some of the dacs are shared between the max9979 channels, and some perform dual functions within a channel (figure 12). important details about the operation of shared dacs are: ? vios share a common dac level for both channels. vios dac simultaneously updates the vios1 andvios2 levels. ? iios share a common dac level for both channels. the iios dac simultaneously updates the iios1 andiios2 levels. ? clamphi_ and vhh_ share a common dac level. the clamphi_/vhh_ dac simultaneously updatesthe clamphi_ and vhh_ levels. note that the vhh_ output is 0 to +13v. if clamphi_ is set to a negative value and the vhh_ mode is selected, the vhh_ out- put limits close to 0v. ? chv_ and ivmax_ share a common dac level. the chv_/ivmax_ dac simultaneously updates thechv_ and ivmax_ levels. ? clv_ and ivmin_ share a common dac level. the clv_/ivmin_ dac simultaneously updates the clv_and ivmin_ levels. a 16-bit code that varies between 0x0000 and 0xffffsets all dac levels. table 20 presents a list of the dacs and their default values. calibrating dac gain and offset dac calibration registers adjust the gain and offset ofeach dac. each dac has at least one calibration regis- ter. all dac calibration registers are programmed with a 14-bit code, except vin_, which uses a 15-bit code (table 19). the codes are divided into two fields, one field each for gain (gcal_) and offset (ocal_). vin_ has a 7- bit field for gain and an 8-bit field for offset. all other dacs have a 6-bit field for gain and an 8-bit field for offset. table 19. data bit assignments* (continued) function dac gain and offset calibration registers bit dcl control register** dcl calibration register** pmu control register** level-setter register vin all others d11 tmux2 = 0 pmu-f bit 11 gcal3 gcal3 d12 tmux3 = 0 pmu-s bit 12 gcal4 gcal4 d13 bit 13 gcal5 gcal5 d14 bit 14 gcal6 d15 bit 15 (msb) *the data bits enter the shift register in the order, msb to lsb. **the dcl control, dcl calibration, and pmu control registers default to 0x0004, 0x0008, and 0x0003 respectively at power-up. clamphi1 clamphi1 channel 1 vhh1chv1 chv1 ivmax1 clv1 clv1 ivmin1iios iios vios max9979 clamphi2 clamphi2 channel 2 vhh2 chv2 chv2 ivmin2 clv2 clv2 ivmax2 iios vios vios figure 12. arrangement of shared dacs downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 53 the vch_, vcl_, and vin_ dacs have duplicate calibra-tion registers that are selected and addressed as a func- tion of the selected dcl/pmu modes. the vch_ and vcl_ registers each have three separate calibration registers that are used by the window comparator, the differential comparator, and the pmu comparator, respectively. the vin_ register features six duplicate cali- bration registers that are selected as a function of the pmu force mode. these registers are individually addressed by first selecting the appropriate mode, then performing the register write. after the calibration regis-ters are programmed, the appropriate register is automat- ically switched in as a function of the operating mode. table 20 presents a list of the dac registers and their default values. calibration registers are programmed to default values only during a power-on reset. asserting rst does not force the calibration registers to their default values. table 21 summarizes the dac registeraddresses. figure 13 shows how the calibration regis- ters affect the dac outputs. table 20. dac power-up and reset default values dac description level-setting register power-up and rst value calibration register power-up value* dhv_ driver high 0x4000 0x2080 dlv_ driver low 0x4000 0x2080 dtv_ driver term 0x4000 0x2080 chv_/ivmax_ high comparator/pmu high comparator 0x4000 0x2080 clv_/ivmin_ low comparator/pmu low comparator 0x4000 0x2080 cphv_ high high-impedance clamp 0x4000 0x2080 cplv_ low high-impedance clamp 0x4000 0x2080 vin_ pmu force value 0x4000 0x4080 vcom_ load commutation voltage 0x4000 0x2080 vldh_ load source current 0x4000 0x2080 vldl_ load sink current 0x4000 0x2080 vios pmu measure voltage offset 0x4000 0x2080 iios pmu force/measure current offset 0x4000 0x2080 clamphi_/vhh_ pmu high clamp/driver super voltage 0x4000 0x2080 clamplo_ pmu low clamp 0x4000 0x2080 * calibration registers not affected by rst . downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 54 ______________________________________________________________________________________ table 21. dac level-setting and calibration register addresses level-setting register address calibration register address dac description ch 0 ch 1 both ch 0 ch 1 both notes dhv_ driver high 0x11 0x21 0x31 0x51 0x61 0x71 dlv_ driver low 0x12 0x22 0x32 0x52 0x62 0x72 dtv_ driver term 0x13 0x23 0x33 0x53 0x63 0x73 chv_/ivmax_ high comparator/pmu high comparator 0x14 0x24 0x34 0x54 0x64 0x74 1, 3 clv_/ivmin_ low comparator/pmu low comparator 0x15 0x25 0x35 0x55 0x65 0x75 2, 3 cphv_ high high-impedance clamp 0x16 0x26 0x36 0x56 0x66 0x76 cplv_ low high-impedance clamp 0x17 0x27 0x37 0x57 0x67 0x77 vin_ pmu force value 0x19 0x29 0x39 0x59 0x69 0x79 3 vcom_ load commutation voltage 0x1a 0x2a 0x3a 0x5a 0x6a 0x7a vldh_ load source current 0x1b 0x2b 0x3b 0x5b 0x6b 0x7b vldl_ load sink current 0x1c 0x2c 0x3c 0x5c 0x6c 0x7c vios pmu measure voltage offset 0x1d 0x5d - 4 iios pmu force/measure current offset 0x2d 0x6d 5 clamphi_/vhh_ pmu high clamp/driver super voltage 0x1e 0x2e 0x3e 0x5e 0x6e 0x7e 3, 6 clamplo_ pmu low clamp 0x1f 0x2f 0x3f 0x5f 0x6f 0x7f note 1: a common dac is used for both the chv_ and ivmax_ levels. note 2: a common dac is used for both the clv_ and ivmin_ levels. note 3: the chv_ and clv_ levels each have a pair of calibration registers. one is active when using the window comparator; theother is active when using the differential comparator. the vin_ level has six calibration registers corresponding to the force voltage and the five ranges of force current modes of the pmu. the clamphi_, vhh_, ivmax_, and ivmin_ levels each have their own dedicated calibration register. addressing any of these calibration registers requires device mode settings (table 22) as well as the registers address. note 4: the vios level is common to both channels. a channel 0 dac is used to generate vios. note 5: the iios level is common to both channels. a channel 1 dac is used to generate iios. note 6: a common dac is used for both the clamphi_ and vhh_ levels. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 55 offset and gain calibration circuit offset and gain calibration circuit chv_ one of four identical circuits shown, for dacs chv_/ivmax_ and clv_/ivmin_ window comparator differential comparator offset and gain calibration circuit one of 22 identical circuits shown, for dacs dhv_, dlv_, dtv_, vcom_, vldh_, vldl_, cphv_, cplv_, clamplo_, vios, and iios offset and gain calibration circuit offset and gain calibration circuit clamphi_ vhh_ 14-bit gain and offset calibration register 14-bit gain and offset calibration register 14-bit gain and offset calibration register 14-bit gain and offset calibration register 14-bit gain and offset calibration register 14-bit gain and offset calibration register 15-bit gain and offset calibration register 15-bit gain and offset calibration register 15-bit gain and offset calibration register 15-bit gain and offset calibration register 15-bit gain and offset calibration register 15-bit gain and offset calibration register offset and gain calibration circuit vin_ fv fi ab cd e ivmax_ vhh_and clamphi_ dacs dhv_ vin_ dacs 16-bit dac 16-bit dac 16-bit dac 16-bit dac figure 13. dac calibration registers downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 56 ______________________________________________________________________________________ an example calibration sequence follows: 1) power up the max9979. this sets the level-setting dacs to their default 0v values, and the gain andoffset calibration registers to their default midscale values (table 20). 2) gain calibration (gain must be calibrated before calibrating offset). a. program a level-setting dac to its minimum value and measure the output voltage(v out_min ). then, reprogram the dac to its maximum value and again measure the outputvoltage (v out_max ). calculate the gain using the following equation: where v set_max and v set_min are the desired gain calibration points. b. set the dacs gain calibration register until the gain is as close to 1 as possible. this cali-brates the gain for the dac. record the gain calibration register value for later use. 3) offset calibration (must be done after the gain cali- bration). a. set the level of the dac to the desired offset calibration point (e.g., midscale). b. measure v out_ and compare it to the expect- ed output. c. adjust the offset calibration register until v out_ is as close as possible to the expected voltage. record the value of the offset calibra-tion register for later use. 4) repeat the above procedure for all dacs that need calibration, recording each of the gain and offsetcalibration register settings for later use. the prior procedure only needs to be done once. eachtime the power is cycled, simply reprogram the gain and offset registers using the recorded values. table 22 presents the mode settings required to access the calibration registers of the shared dacs. in some cases there is more than one way to access the register. gain vv vv out max out min set max set min = ____ table 22. mode-control settings to access calibration registers of shared dacs calibration register serial-interface bits rs_ bit dac mode hizforce_ differential1 fmode_ mmode_ 210 window 0 0 x x x x x clv_, chv_ differential 0 1 x x x x x ivmax_, ivmin_ 1 x x x x x x clamphi_ 1 x x x x x x vhh_ 0 x x x x x x 0xx 0 fv* 1x0 x xxx fi range a 1 x 1 x 1 x x 0xx 1 1 x x 0xx 1 fi range b* 1x1 x 011 0xx 1 fi range c* 1x1 x 010 0xx 1 fi range d* 1x1 x 001 0xx 1 vin_ fi range e* 1x1 x 000 * any of these conditions allow access to the calibration register. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 57 dac output level transfer functions each of the max9979 analog dac levels is set with atransfer function that includes the 16-bit dac code set- ting, the gain code setting, and the offset code setting. the v dac and v vindac expressions below present the basic dac transfer functions. each dac has a voltageoutput range of -2.5v to +7.5v (typ). thirteen of these dacs are identical and generate a potential according to the following equation: a separate dac (vin_) is used for the pmu force value.this dac has a finer gain adjustment resolution and fol- lows the equation: for all dacs, the offset code is an integer value between 0 and 255. the vin_dac gain code is an integer value between 0 and 127, and for all other dacs the gain code is an integer value between 0 and 63. offset and gain codes are based on the calibration register settings. v dac vv o vindac code ref dgs = ? ? ? ? ? ? () + 16384 1 f ffset code () ? ? ? ? ? ? ? ? ? ? + 0 001 0 128 098 0 .. .. 0 02 64 ? ? ? ? ? ? ? ? ? ? ? ? + gain v code dgs v dac vv offse dac code ref dgs = ? ? ? ? ? ? () + 16384 1 tt g code () ? ? ? ? ? ? ? ? ? ? + 0 001 0 128 098 002 .. .. a ain v code dgs 32 ? ? ? ? ? ? ? ? ? ? ? ? + table 23. dac transfer functions level level transfer function dhv_ v dac x dhv_ gain + dhv_ offset dlv_ v dac x dlv_ gain + dlv_ offset dtv_ v dac x dtv_ gain + dtv_ offset chv_ v dac x chv_ gain + chv_ offset ivmax_ v dac x ivmax_ gain + ivmax_ offset clv_ v dac x clv_ gain + clv_ offset ivmin_ v dac x ivmin_ gain + ivmin_ offset cphv_ v dac x cphv_ gain + cphv_ offset cplv_ v dac x cplv_ gain + cplv_ offset vin_ (fvmi) v vindac x pmu_fv_ gain + pmu_fv_ offset vin_ (fimv 50ma) (v vindac - v iios ) x (50ma/4v) x pmu_fi_ gain + pmu_fi_ offset vin_ (fimv 2ma) (v vindac - v iios ) x (2ma/4v) x pmu_fi_ gain + pmu_fi_ offset vin_ (fimv 200_a) (v vindac - v iios ) x (200_a/4v) x pmu_fi_ gain + pmu_fi_ offset vin_ (fimv 20_a) (v vindac - v iios ) x (20_a/4v) x pmu_fi_ gain + pmu_fi_ offset vin_ (fimv 2_a) (v vindac - v iios ) x (2_a/4v) x pmu_fi_ gain + pmu_fi offset vcom_ v dac x vcom_ gain + vcom_ offset vldh_ (v dac - dgs) x (20ma/6v) x vldh_ gain + vldh_ offset vldl_ (v dac - dgs) x (20ma/6v) x vldl_ gain + vldl_ offset vios ((v dac + dgs)/2) x vios gain + vios offset iios ((v dac + ref)/2) x iios gain + iios offset vhh_ (v dac - dgs) x 2 x vhh_ gain + vhh_ offset + dgs clamphi_ (voltage) v dac x clamphi_ gain + clamphi_ offset clamphi_ (current) (v dac - v iios ) x fsr/2v x clamphi_ gain + clamphi_ offset clamplo_ (voltage) v dac x clamplo_ gain + clamplo_ offset clamplo_ (current) (v dac - v iios ) x fsr/2v x clamp_lo_ gain + clamplo_ offset ? values for pmu_fi_ gain and pmu_fi_ offset are different for each pmu current range. ? vldh_ and vldl_ levels less than zero are truncated. ? full-scale range is dependent upon the pmu current range. values are 100ma, 4ma, 400a, 40a, and 4a for rangesaCe, respectively. ? values for clamphi_ gain, clamplo_ gain, clamphi_ off- set, and clamplo_ offset vary with pmu force mode andcurrent range. downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs 58 ______________________________________________________________________________________ the v dac voltages are then utilized for the various sig- nal paths within the max9979 (i.e., driver level dhv_).each of these signal paths have inherent gain and offset errors, denoted as _gain and _offset terms in the level transfer function column in table 23. these error terms are presented to convey the non-ideal gain and offset of the signal pathsthey do not have a specified value. the gain code and offset code features of each dac are designed to correct for these errors to makethe level transfer function expressions, and therefore, the final signal path outputs (e.g., dhv_) more ideal. applications information device power-up state upon power-up, the dcl enters low-leak mode and thepmu enters high-impedance mode. the dcl control, dcl calibration, and pmu control registers default to 0x0004, 0x0008, and 0x0003, respectively. for initialpower-up values for the level-setting registers, see table 20. power supplies may be powered on in any sequence. power-supply considerations bypass each supply input to gnd and ref to dgs with0.1f capacitors (figure 13). additionally, use bulk bypassing of at least 10f where the power-supply connections meet the circuit board. exposed pad the exposed pad is internally connected to ground.connect to a open copper pcb ground plane or heatsink to maximize thermal performance. not intend- ed as an electrical connection point. 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 din v ee tqfn-ep-idp top view 52 53 v cc lleakp1 hizmeasp1 rcv1 nrcv1 ndata1 bv1 envhhp1 data1 cl1 ncl1 nch1 ctv1 ch1 v ee v cc pmu-spmu-f v hhp n.c.temp v cc v ee dut1 35 36 37 v cc v ee gnd sclk *ep *ep = exposed pad. cs dgnd dout gnd duthi1 dutlo1 rst load v dd dgs ref dutlo0 duthi0 48 dut0 meas0 64 65 66 67 68 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 sense1 n.c. 34 33 49 50 v ee v cc 51 gnd 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 + meas1 17 max9979 v ee v cc lleakp0 hizmeasp0 rcv0 nrcv0ndata0 bv0envhhp0 data0cl0 ncl0nch0 ctv0ch0 sense0 n.c. pin configuration downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs ______________________________________________________________________________________ 59 chip information process: bicmos 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 din v ee 52 53 v cc lleakp1 hizmeasp1 rcv1 nrcv1ndata1 bv1envhhp1 data1cl1 ncl1nch1 ctv1ch1 v ee v cc pmu-s pmu-f v hhp n.c. temp v cc v ee dut1 35 36 37 v cc v ee gnd sclk cs dgnd dout 2 x 1000 0.1 f 0.1 f +3.3v to dut ground to other max9979s 0.1 f 0.1 f 0.1 f0 . 1 f 0.1 f 0.1 f +3.5v +1.4v 4 x 50 4 x 50 gndduthi1 dutlo1 rst load v dd dgs ref dutlo0 duthi0 48 dut0 meas0 64 65 66 67 + 68 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 sense1n.c. 34 33 49 50 v ee v cc 51 gnd 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 meas1 17 max9979 v ee v cc lleakp0 hizmeasp0 rcv0 nrcv0 ndata0 bv0 envhhp0 data0 cl0 ncl0 nch0 ctv0 ch0 sense0 n.c. 2.2 f2 . 2 f 0.1 f 0.1 f 0.1 f 2 x 1000 +9.75v +3.5v +17.5v -4.75v +1.4v max6225 typical operating circuit package information for the latest package outline information and land patterns(footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 68 tqfn-ep-idp t6800rn+6 21-0192 90-0090 downloaded from: http:///
max9979 dual 1.1gbps pin electronics with integrated pmu and level-setting dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 60 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/08 initial release 1 10/08 corrected error in table 2 and formula on page 57 36, 57 2 12/08 added new tables 6 and 7 and renumbered subsequent tables 37, 38, 41, 42, 44, 45, 46, 48, 50C54, 56, 57, 58 3 4/09 made spec changes and clarifications 5C8, 20, 57 4 6/09 corrected typical operating circuit 59 5 1/11 updated pin description, exposed pad section, and package information 33, 58, 59 6 8/11 clarified use of exposed die attach pad 33, 58 downloaded from: http:///

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